Learning device and learning method

ABSTRACT

A learning device includes a learning unit configured to learn a model using learning data stored in a data storage unit; a subsampling unit configured to determine whether to use the learning data corresponding to gradient information updated by an update unit based on the model, for learning of a next model after learning of one model based on a subsampling rate; first and second buffer unit configured to buffer learning data determined to be used for and data determined not to be used for learning of the next model and gradient information corresponding to the learning data, respectively, up to a volume determined in advance. The first buffer unit and the second buffer unit are configured to write the learning data and the gradient information into the data storage unit for each predetermined block when buffering the learning data and the gradient information up to the volume.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2019-130620, filed on Jul. 12, 2019. The contents of which are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a learning device, and a learning method.

2. Description of the Related Art

In recent years, an attempt to replace a function of human beings with a large amount of data has been made in various fields by using machine learning that is generally known in relation to artificial intelligence (AI). This field is still greatly developing day by day, but there are some problems under present circumstances. Representative examples thereof include a limit of accuracy including generalization performance for retrieving versatile knowledge from data, and a limit of processing speed due to a large calculation load thereof. As a well-known algorithm for high-performance machine learning, there are known Deep learning (DL), a convolutional neural network (CNN) in which an input vector is limited to the periphery, and the like. As compared with these methods, under present circumstances, gradient boosting (for example, Gradient Boosting Decision Tree (GBDT)) is known to have poor accuracy for input data such as an image, a voice, and a language because it is difficult to extract a feature amount, but give higher performance for other structured data. As a matter of fact, in Kaggle as a competition of data scientists, the GBDT is the most standard algorithm. In the real world, 70% of problems that are desired to be solved by machine learning is said to be structured data other than an image, a voice, and a language, so that there is no doubt that the GBDT is an important algorithm to solve the problems in the real world. Additionally, in recent years, there has been developed a method of extracting a feature from data such as an image and a voice using a decision tree.

In the gradient boosting, learning processing is performed at higher speed than deep learning such as CCN. However, it is fairly common to perform learning several hundreds of times or more for adjustment of hyperparameter and feature selection as required work in a practical use, and for work such as model ensemble and stacking for improving performance by combining a plurality of models for the purpose of evaluating generalization performance and improving performance. Thus, a calculation time becomes a problem even in the gradient boosting the processing of which is performed at relatively high speed. Thus, in recent years, there have been reported a large number of researches for increasing a processing speed of learning processing by gradient boosting.

To implement such discrimination using a decision tree, there is disclosed a technique of enhancing an effect of a cache memory and increasing speed thereof by properly adjusting a threshold (refer to Japanese Patent No. 5032602).

In the technique disclosed in Japanese Patent No. 5032602, it is estimated that processing time is long because an optimal branch condition is calculated for each node, and pieces of processing of causing certain sample data at a node to branch are performed in order based on the branch condition, so that a static random access memory (SRAM) that enables random access is basically used as a memory storing the sample data to shorten the processing time. However, if the SRAM inside a chip is used as a memory for storing the sample data, there is the problem that only a small amount of data can be handled, and a large amount of sample data cannot be handled. For example, after one model is learned in gradient boosting, what is called data subsampling is performed for calculating and updating gradient information corresponding to each sample data and extracting the sample data used for learning of the next model. In a case of using the SRAM for storing the sample data in such processing, there is the problem that processing for a large amount of sample data cannot be performed.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a learning device is configured to perform learning by gradient boosting. The learning device includes a data storage unit, a learning unit, an update unit, a subsampling unit, a first buffer unit, and a second buffer unit. The data storage unit is configured to store learning data for learning a model by the gradient boosting and gradient information corresponding to the learning data. The learning unit is configured to learn the model using the learning data stored in the data storage unit. The update unit is configured to update gradient information of each learning data based on the model learned by the learning unit. The subsampling unit is configured to determine whether to use the learning data corresponding to the gradient information updated by the update unit, for learning of a next model after learning of one model based on a subsampling rate as a ratio of learning data used for learning of the model. The first buffer unit is configured to buffer learning data determined to be used for learning of the next model by the subsampling unit and gradient information corresponding to the learning data up to a volume determined in advance. The second buffer unit is configured to buffer learning data determined not to be used for learning of the next model by the subsampling unit and gradient information corresponding to the learning data up to the volume determined in advance. The first buffer unit and the second buffer unit are configured to write the learning data and the gradient information into the data storage unit for each predetermined block when buffering the learning data and the gradient information up to the volume determined in advance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example of a decision tree model;

FIG. 2 is a diagram illustrating an example of a module configuration of a learning and discrimination device according to a first embodiment;

FIG. 3 is a diagram illustrating an example of a configuration of a pointer memory;

FIG. 4 is a diagram illustrating an example of a module configuration of a learning module;

FIG. 5 is a diagram illustrating an operation of a module at the time of initializing the learning and discrimination device according to the first embodiment;

FIG. 6 is a diagram illustrating an operation of a module in a case of determining node parameters at depth 0, node 0 of the learning and discrimination device according to the first embodiment;

FIG. 7 is a diagram illustrating an operation of a module at the time of branching at depth 0, node 0 of the learning and discrimination device according to the first embodiment;

FIG. 8 is a diagram illustrating an operation of a module in a case of determining node parameters at depth 1, node 0 of the learning and discrimination device according to the first embodiment;

FIG. 9 is a diagram illustrating an operation of a module at the time of branching at depth 1, node 0 of the learning and discrimination device according to the first embodiment;

FIG. 10 is a diagram illustrating an operation of a module in a case of determining node parameters at depth 1, node 1 of the learning and discrimination device according to the first embodiment;

FIG. 11 is a diagram illustrating an operation of a module at the time of branching at depth 1, node 1 of the learning and discrimination device according to the first embodiment;

FIG. 12 is a diagram illustrating an operation of a module in a case in which branching is not performed as a result of determining node parameters at depth 1, node 1 of the learning and discrimination device according to the first embodiment;

FIG. 13 is a diagram illustrating an operation of a module at the time of updating state information of all pieces of sample data in a case in which learning of a decision tree is completed by the learning and discrimination device according to the first embodiment;

FIG. 14 is a diagram illustrating an example of a configuration of a model memory of a learning and discrimination device according to a modification of the first embodiment;

FIG. 15 is a diagram illustrating an example of a configuration of a classification module of the learning and discrimination device according to the modification of the first embodiment;

FIG. 16 is a diagram illustrating an example of a module configuration of the learning and discrimination device to which Data Parallel is applied;

FIG. 17 is a diagram illustrating an example of a specific module configuration of a learning module;

FIG. 18 is a diagram illustrating an example of a module configuration of a gradient histogram calculating module of the learning module;

FIG. 19 is a diagram illustrating an example of a module configuration of an accumulated gradient calculating module of the learning module;

FIG. 20 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module in a case in which Data Parallel is implemented;

FIG. 21 is a diagram illustrating an example of a module configuration of a learning module of a learning and discrimination device according to a second embodiment;

FIG. 22 is a diagram illustrating an example of a module configuration of a gradient histogram calculating module of the learning module according to the second embodiment;

FIG. 23 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module in a case in which the number of division is assumed to be 3 in the learning module according to the second embodiment;

FIG. 24 is a diagram illustrating an example of a module configuration of an accumulated gradient calculating module of the learning module according to the second embodiment;

FIG. 25 is a diagram illustrating an example of a module configuration of the learning module in a case in which the number of types of feature amounts is assumed to be 2 in the learning and discrimination device according to the second embodiment;

FIG. 26 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module in a case in which the number of types of feature amounts is assumed to be 2 in the learning module according to the second embodiment;

FIG. 27 is a diagram illustrating an example of a module configuration of a learning and discrimination device according to a third embodiment;

FIG. 28 is a diagram for explaining address calculation for learning data at a node as the next learning target;

FIG. 29 is a diagram illustrating an example of a module configuration of an address manager according to the third embodiment;

FIG. 30 is a diagram illustrating an example of a module configuration of an address calculator 121 according to the third embodiment;

FIG. 31 is a diagram for explaining a node address;

FIG. 32 is a diagram illustrating an example of a configuration of an address memory according to the third embodiment;

FIG. 33 is a diagram illustrating a state of the address memory before learning at depth 0, node 0 performed by the learning and discrimination device according to the third embodiment;

FIG. 34 is a diagram illustrating a state of the address memory after learning at depth 0, node 0 performed by the learning and discrimination device according to the third embodiment;

FIG. 35 is a diagram illustrating a state of the address memory after learning at depth 1, node 0 performed by the learning and discrimination device according to the third embodiment;

FIG. 36 is a diagram illustrating a state of the address memory after learning at depth 1, node 1 performed by the learning and discrimination device according to the third embodiment;

FIG. 37 is a diagram illustrating a state of the address memory after learning at depth 2, node 0 performed by the learning and discrimination device according to the third embodiment;

FIG. 38 is a diagram illustrating an example of a module configuration for implementing Data Parallel for the learning and discrimination device according to the third embodiment;

FIG. 39 is a diagram illustrating a configuration for explaining a function of the address manager in a case of implementing Data Parallel for the learning and discrimination device according to the third embodiment;

FIG. 40 is a diagram illustrating an example of a module configuration of a learning and discrimination device according to a fourth embodiment to which Data Parallel is applied;

FIG. 41 is a diagram illustrating a configuration in a case in which the number of AUC calculators is assumed to be 1 for Data Parallel;

FIG. 42 is a diagram illustrating a configuration of including the AUC calculator for each division for Data Parallel;

FIG. 43 is a diagram illustrating a configuration of a principal part of the learning and discrimination device according to the fourth embodiment;

FIG. 44 is a diagram illustrating an example of a comparison result of processing time between a case in which one AUC calculator is provided and a case in which the AUC calculator is provided for each division;

FIG. 45 is a diagram illustrating an example of a comparison result of processing time between a case in which one model memory is provided and a case in which the model memory is provided for each division;

FIG. 46 is a diagram illustrating an example of the entire configuration of a learning and discrimination device according to a fifth embodiment;

FIG. 47 is a diagram illustrating an example of a module configuration of one learning unit of the learning and discrimination device according to the fifth embodiment;

FIG. 48 is a diagram illustrating an example of a mode of storing sample data in an external memory of the learning and discrimination device according to the fifth embodiment;

FIG. 49 is a diagram illustrating an example of the entire configuration of a learning and discrimination device according to a sixth embodiment;

FIG. 50 is a diagram illustrating an example of a configuration of a subsampling unit of the learning and discrimination device according to the sixth embodiment; and

FIG. 51 is a diagram illustrating an example of a module configuration of one learning unit of the learning and discrimination device according to the sixth embodiment.

The accompanying drawings are intended to depict exemplary embodiments of the present invention and should not be interpreted to limit the scope thereof. Identical or similar reference numerals designate identical or similar components throughout the various drawings.

DESCRIPTION OF THE EMBODIMENTS

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention.

As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In describing preferred embodiments illustrated in the drawings, specific terminology may be employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that have the same function, operate in a similar manner, and achieve a similar result.

An embodiment of the present invention will be described in detail below with reference to the drawings.

An embodiment has an object to provide a learning device and a learning method that can perform data subsampling for a large amount of sample data in the gradient boosting.

The following describes embodiments of a learning device and a learning method according to the present invention in detail with reference to figures. The present invention is not limited to the following embodiments. Components in the following embodiments encompass a component that is easily conceivable by those skilled in the art, substantially the same component, and what is called an equivalent. Additionally, the components can be variously omitted, replaced, modified, and combined without departing from the gist of the embodiments described below.

First Embodiment

Regarding Logic of GBDT

In DL as an algorithm of high-performance machine learning, a discriminator is attempted to be implemented by various kinds of hard logic, which has been found to have higher power efficiency as compared with processing using a graphics processing unit (GPU). However, an architecture of the GPU closely matches to especially a CNN in the field of DL, so that, in view of speed, speed of discrimination performed by a field-programmable gate array (FPGA) implemented with logic is not higher than that of the GPU. On the other hand, hard logic has been attempted to be implemented by FPGA on a decision tree-based algorithm such as a GBDT, and a result of higher speed than the GPU has been reported. This is because, as described later, the decision tree-based algorithm is not appropriate for the architecture of the GPU in view of a feature of data arrangement thereof.

Examination as to learning falls behind examination as to discrimination in the world. There is almost no report about present circumstances of DL, and the number of reports about a decision tree system is small. Particularly, there is no report about learning by the GBDT under present circumstances, which can be currently considered to be an undeveloped field. To obtain an accurate discrimination model, selection and design of a feature amount, and selection of a hyperparameter of a learning algorithm are performed at the time of learning, so that an enormous number of trials are required. Especially in a case in which there is a large amount of learning data, speed of learning processing considerably affects accuracy of a final model practically. Additionally, in a field in which real-time performance for following environmental change is required such as robotics, High Frequency Trading (HFT), and Real-Time Bidding (RTB), speed is directly connected with performance. Thus, in a case in which high-speed learning processing is achieved by the GBDT with high accuracy, it can be considered to be able to largely improve performance of a system using the GBDT eventually.

Affinity of GBDT for FPGA

The following describes, in view of affinity of the GBDT for the FPGA, why the processing speed of the decision tree or the GBDT by the GPU is not high, and why the processing speed thereof by the FPGA is high.

First, description is made from a viewpoint that the GBDT is an algorithm using boosting. In a case of Random Forest (RF) using ensemble learning in the field of decision tree, trees are not dependent on each other, so that parallelization is easily performed by the GPU. However, the GBDT is a method of connecting a large number of trees using boosting, so that learning of a subsequent tree cannot be started until a result of a previous tree is obtained. Thus, the processing is serial processing, and it is important to learn each tree at high speed as much as possible. On the other hand, in the RF, an option of increasing the entire learning speed may be employed by increasing learning speed for a large number of trees in parallel even if the learning speed for each tree is low. Thus, also in a case of using the GPU, it can be considered that a problem of access latency of a Dynamic Random Access Memory (DRAM) (described later) can be concealed in some degree.

Next, description is made from a viewpoint of a limit of access speed (especially in random access) of a GPU device to a random access memory (RAM). A static random access memory (SRAM) built into the FPGA can greatly increase a bus width of a RAM in the FPGA, so that 400 [GB/sec] is achieved as follows even in a case of using XC7k325T manufactured by Xilinx Inc. as a middle-range FPGA, for example. Capacity of a built-in RAM is 16 [Mb]. 445 BRAMs×36 bits×100 MHz×2 ports=445*36*2*100*10{circumflex over ( )}6/10{circumflex over ( )}9=400 GB/sec

In a case of using VU9P manufactured by Xilinx Inc. as a high-end FPGA, 864 [GB/sec] is achieved. The capacity of the built-in RAM is 270 [Mb]. 960URAMs×36 bits×100 MHz×2 ports=960*36*2*100*10{circumflex over ( )}6/10{circumflex over ( )}9=864 GB/sec

These values are obtained in a case of causing a clock frequency to be 100 [MHz], but actually, operation may be performed at about 200 to 500 [MHz] by devising a circuit configuration, and a limit band is raised several-fold. On the other hand, a RAM of a current generation connected to a central processing unit (CPU) is Double-Data-Rate4 (DDR4), but a band generated with one Dual Inline Memory Module (DIMM) remains at 25.6 [GB/sec] as described below. Even with an interleave configuration (256 bit width) of four DIMMs, the band reaches about 100 [GB/sec]. In a case in which a chip standard of the DDR4 is DDR4-3200 (bus width of 64 bit, 1 DIMM), the following expression is satisfied. 1600 MHz×2(DDR)×64=1600*10{circumflex over ( )}6*2*64/10{circumflex over ( )}9=25.6 GB/sec

A band of a Graphics Double-Data-Rate 5 (GDDR5) mounted on the GPU is about four times larger than the band of the DDR4, but is about 400 [GB/sec] at the maximum.

In this way, the bands are greatly different from each other between the RAM in the FPGA and an external memory of the GPU and the CPU. Although the case of sequential access to an address has been described above, access time at the time of random access works more greatly. The built-in RAM of the FPGA is an SRAM, so that the access latency is 1 clock both in the sequential access and the random access. However, each of the DDR4 and the GDDR5 is a DRAM, so that latency is increased in a case of accessing different columns due to a sense amplifier. For example, typical Column Address Strobe latency (CAS latency) is 16 clock in the RAM of the DDR4, and throughput is calculated to be 1/16 of that of the sequential access in brief.

In a case of the CNN, pieces of data of adjacent pixels are successively processed, so that latency of the random access is not a big problem. However, in a case of the decision tree, addresses of original data of respective branches become discontinuous as branching proceeds, which becomes random access basically. Thus, in a case of storing the data in the DRAM, the throughput thereof causes a bottleneck, and the speed is greatly lowered. The GPU includes a cache to suppress performance deterioration in such a case, but the decision tree is basically an algorithm of accessing the entire data, so that there is no locality in data access, and an effect of the cache is hardly exhibited. In the structure of the GPU, the GPU includes a shared memory including an SRAM assigned to each arithmetic core (SM), and high-speed processing can be performed by using the shared memory in some cases. However, in a case in which the capacity of each SM is small, that is, 16 to 48 [kB], and access is performed across SMs, large latency is caused. The following represents a test calculation of the capacity of the shared memory in a case of Nvidia K80 as an expensive large-scale GPU at the present time. K80=2×13 SMX=26 SMX=4992 CUDA core 26×48×8=9 Mb

As described above, even in a large-scale GPU that is worth hundreds of thousands of yen, the capacity of the shared memory is only 9 [Mb], which is too small. Additionally, in a case of the GPU, as described above, because the SM that performs processing cannot directly access the shared memory of the other SM, there is a restriction that high-speed coding is difficult to be performed in a case of being used for learning of the decision tree.

As a described above, assuming that the data is stored in the SRAM on the FPGA, it can be considered that the FPGA can implement a learning algorithm of the GBDT at higher speed as compared with the GPU.

Algorithm of GBDT

FIG. 1 is a diagram illustrating an example of a decision tree model. The following describes basic logic of the GBDT with reference to expressions (1) to (22) and FIG. 1 .

The GBDT is a method of supervised learning, and the supervised learning is processing of optimizing an objective function obj(θ) including a loss function L(θ) representing a degree of fitting with respect to learning data and a regularization term Ω(θ) representing complexity of a learned model using some kind of scale as represented by the following expression (1). The regularization term Ω(θ) has a role of preventing a model (decision tree) from being too complicated, that is, improving generalization performance. obj(θ)=L(θ)+Ω(θ)  (1)

The loss function of the first term of the expression (1) is, for example, obtained by adding up losses calculated from an error function 1 for respective pieces of sample data (learning data) as represented by the following expression (2). In this case, n is the number of pieces of sample data, i is a sample number, y is a label, and y (hat) of a model is a predicted value.

$\begin{matrix} {{L(\theta)} = {\sum\limits_{i = 1}^{D}{l\left( {y_{i},{\hat{y}}_{i}} \right)}}} & (2) \end{matrix}$

In this case, for example, as the error function 1, a square error function or a logistic loss function as represented by the following expression (3) and the expression (4) is used. l(y _(i) ,ŷ _(i))=(y _(i) −ŷ _(i))²  (3) l(y _(i) ,ŷ _(i))=y _(i) ln(1+e ^(−ŷ) ^(i) )+(1−y _(i))ln(1+e ^(ŷ) ^(i) )  (4)

As the regularization term Ω(θ) of the second term of the expression (1), for example, a squared norm of a parameter θ as represented by the following expression (5) is used. In this case, λ is a hyperparameter representing weight of regularization. Ω(θ)=λ∥θ∥²  (5)

A case of the GBDT is considered herein. First, the predicted value for the i-th sample data x_(i) of the GBDT can be represented by the following expression (6).

$\begin{matrix} {{\hat{y}}_{i} = {\sum\limits_{k = 1}^{K}{f_{k}\left( x_{i} \right)}}} & (6) \end{matrix}$

In this case, K is the total number of decision trees, k is a number of the decision tree, f_(k)( ) is an output of the k-th decision tree, and x_(i) is a feature amount of sample data to be input. Accordingly, it can be found that a final output is obtained by adding up outputs of the respective decision trees in the GBDT similarly to the RF and the like. The parameter θ is represented as θ={f₁, f₂, . . . , f_(K)}. According to the above description, the objective function of the GBDT is represented by the following expression (7).

$\begin{matrix} {{{obj}(\theta)} = {{\sum\limits_{i = 1}^{n}{l\left( {y_{i},{\hat{y}}_{i}} \right)}} + {\sum\limits_{k = 1}^{K}{\Omega\left( f_{k} \right)}}}} & (7) \end{matrix}$

Learning is performed on the objective function described above, but a method such as Stochastic Gradient Descent (SGD) used for learning of a neural network and the like cannot be used for the decision tree model. Thus, learning is performed by using Additive Training (boosting). In the Additive Training, a predicted value in a certain round (number of times of learning, the number of decision tree models) t is represented by the following expression (8).

$\begin{matrix} {{{\hat{y}}_{i}^{(0)} = 0}{{\hat{y}}_{i}^{(1)} = {{f_{1}\left( x_{i} \right)} = {{\hat{y}}_{i}^{(0)} + {f_{1}\left( x_{i} \right)}}}}{{\hat{y}}_{i}^{(2)} = {{{f_{1}\left( x_{i} \right)} + {f_{2}\left( x_{i} \right)}} = {{\hat{y}}_{i}^{(1)} + {f_{2}\left( x_{i} \right)}}}}{{\hat{y}}_{i}^{(t)} = {{\sum\limits_{k = 1}^{t}{f_{k}\left( x_{i} \right)}} = {{\hat{y}}_{i}^{({t - 1})} + {f_{t}\left( x_{i} \right)}}}}} & (8) \end{matrix}$

From the expression (8), it can be found that (an output) of the decision tree f_(t)(x_(i)) needs to be obtained in the certain round t. On the other hand, it is not required to consider other rounds in the certain round t. Thus, the following description considers the round t. The objective function in the round t is represented by the following expression (9).

$\begin{matrix} {{obj}^{(t)} = {{{\sum\limits_{i = 1}^{n}{l\left( {y_{i},{\hat{y}}_{i}^{(t)}} \right)}} + {\sum\limits_{k = 1}^{K}{\Omega\left( f_{k} \right)}}}\mspace{56mu} = {{\sum\limits_{i = 1}^{n}{l\left( {y_{i},{{\hat{y}}_{i}^{(t)} + {f_{t}\left( x_{i} \right)}}} \right)}} + {\Omega\left( f_{k} \right)} + {constant}}}} & (9) \end{matrix}$

In this case, Taylor expansion (truncated at a second-order term) of the objective function in the round t is represented by the following expression (10).

$\begin{matrix} {{obj}^{(t)} \cong {{\sum\limits_{i = 1}^{n}\left\lbrack {{l\left( {y_{i},{\hat{y}}_{i}^{({t - 1})}} \right)} + {g_{i}{f_{t}\left( x_{i} \right)}} + {\frac{1}{2}h_{i}{f_{t}^{2}\left( x_{i} \right)}}} \right\rbrack} + {\Omega\left( f_{t} \right)} + {constant}}} & (10) \end{matrix}$

In this case, in the expression (10), pieces of gradient information g_(i) and h_(i) are represented by the following expression (11). g _(i)=∂_(ŷ) _(i) _((t-1)) l(y _(i) ,ŷ _(i) ^((t-1))) h _(i)=∂_(ŷ) _(i) _((t-1)) ² l(y _(i) ,ŷ _(i) ^((t-1)))  (11)

When a constant term is ignored in the expression (10), the objective function in the round t is represented by the following expression (12).

$\begin{matrix} {{obj}^{(t)} = {{\sum\limits_{i = 1}^{n}\left\lbrack {{g_{i}{f_{t}\left( x_{i} \right)}} + {\frac{1}{2}h_{i}{f_{t}^{2}\left( x_{i} \right)}}} \right\rbrack} + {\Omega\left( f_{t} \right)}}} & (12) \end{matrix}$

In the expression (12), the objective function in the round t is represented by the regularization term and a value obtained by performing first-order differentiation and second-order differentiation on the error function by the predicted value in a previous round, so that it can be found that the error function on which first-order differentiation and second-order differentiation can be performed can be applied.

The following considers the decision tree model. FIG. 1 illustrates an example of the decision tree model. The decision tree model includes nodes and leaves. At the node, an input is input to the next node or leaf under a certain branch condition, and the leaf has a leaf weight, which becomes an output corresponding to the input. For example, FIG. 1 illustrates the fact that a leaf weight W2 of a “leaf 2” is “−1”.

The decision tree model is formulated as represented by the following expression (13). f _(t)(x)=w _(q(x)) ,w∈

^(T) ,q:

^(d)→{1,2, . . . T}   (13)

In the expression (13), w represents a leaf weight, and q represents a structure of the tree. That is, an input (sample data x) is assigned to any of the leaves depending on the structure q of the tree, and the leaf weight of the leaf is output.

In this case, complexity of the decision tree model is defined as represented by the following expression (14).

$\begin{matrix} {{\Omega\left( f_{t} \right)} = {{\gamma T} + {\frac{1}{2}\lambda{\sum\limits_{j = 1}^{T}w_{j}^{2}}}}} & (14) \end{matrix}$

In the expression (14), the first term represents complexity due to the number of leaves, and the second term represents a squared norm of the leaf weight. γ is a hyperparameter for controlling importance of the regularization term. Based on the above description, the objective function in the round t is organized as represented by the following expression (15).

$\begin{matrix} \begin{matrix} {{obj}^{(t)} \cong {{\sum\limits_{i = 1}^{n}\left\lbrack {{g_{i}{f_{t}\left( x_{i} \right)}} + {\frac{1}{2}h_{i}{f_{t}^{2}\left( x_{i} \right)}}} \right\rbrack} + {\Omega\left( f_{t} \right)}}} \\ {= {{\sum\limits_{i = 1}^{n}\left\lbrack {{g_{i}{w_{q}\left( x_{i} \right)}} + {\frac{1}{2}h_{i}w_{q{(x_{i})}}^{2}}} \right\rbrack} + {\gamma\; T} + {\frac{1}{2}\lambda{\sum\limits_{j = 1}^{T}w_{j}^{2}}}}} \\ {= {{\sum\limits_{j = 1}^{T}\left\lbrack {{\left( {\sum_{i \in {Ij}}g_{i}} \right)w_{j}} + {\frac{1}{2}\left( {{\sum_{i \in {Ij}}h_{i}} + \lambda} \right)w_{j}^{2}}} \right\rbrack} + {\gamma\; T}}} \\ {= {{\sum\limits_{j = 1}^{T}\left\lbrack {{G_{j}w_{j}} + {\frac{1}{2}\left( {H_{j} + \lambda} \right)w_{j}^{2}}} \right\rbrack} + {\gamma\; T}}} \end{matrix} & (15) \end{matrix}$

However, in the expression (15), I_(j), G_(j), and H_(j) are represented by the following expression (16). I _(j) ={i|q(x _(i))=j} G _(j)=Σ_(i∈I) _(j) g _(i) H _(j)=Σ_(i∈I) _(j) h _(i)  (16)

From the expression (15), the objective function in the certain round t is a quadratic function related to the leaf weight w, and a minimum value of the quadratic function and a condition thereof are typically represented by the following expression (17).

$\begin{matrix} {{{{{{argmin}_{w}{Gw}} + {\frac{1}{2}{Hw}^{2}}} = {- \frac{G}{H}}},{H > 0}}{{{\min_{w}{Gw}} + {\frac{1}{2}{Hw}^{2}}} = {{- \frac{1}{2}}\frac{G^{2}}{H}}}} & (17) \end{matrix}$

That is, when the structure q of the decision tree in the certain round t is determined, the objective function and the leaf weight thereof are represented by the following expression (18).

$\begin{matrix} {{w_{j}^{*} = \frac{G_{j}}{H_{j} + \lambda}}{{obj} = {{{- \frac{1}{2}}{\sum\limits_{j = 1}^{T}\frac{G_{j}^{2}}{H_{j} + \lambda}}} + {\gamma\; T}}}} & (18) \end{matrix}$

At this point, the leaf weight is enabled to be calculated at the time when the structure of the decision tree is determined in the certain round. The following describes a procedure of learning the structure of the decision tree.

Methods of learning the structure of the decision tree include a greedy method (Greedy Algorithm). The greedy method is an algorithm of starting the tree structure from depth 0, and learning the structure of the decision tree by calculating a branch score (Gain) at each node to determine whether to branch. The branch score is obtained by the following expression (19).

$\begin{matrix} {{Gain} = {{\frac{1}{2}\left\lbrack {\frac{G_{L}^{2}}{H_{L} + \lambda} + \frac{G_{R}^{2}}{H_{R} + \lambda} - \frac{\left( {G_{L} + G_{R}} \right)^{2}}{H_{L} + H_{R} + \lambda}} \right\rbrack} - \gamma}} & (19) \end{matrix}$

In this case, each of G_(L) and H_(L) is the sum of the gradient information of the sample branching to a left node, each of G_(R) and H_(R) is the sum of the gradient information of the sample branching to a right node, and γ is the regularization term. The first term in [ ] of the expression (19) is a score (objective function) of the sample data branching to the left node, the second term is a score of the sample data branching to the right node, and the third term is a score in a case in which the sample data does not branch, which represents a degree of improvement of the objective function due to branching.

The branch score represented by the expression (19) described above represents goodness at the time of branching with a certain threshold of a certain feature amount, but an optimum condition cannot be determined based on the single branch score. Thus, in the greedy method, the branch score is obtained for all threshold candidates of all feature amounts to find a condition under which the branch score is the largest. The greedy method is a very simple algorithm as described above, but calculation cost thereof is high because the branch score is obtained for all threshold candidates of all feature amounts. Thus, for library such as XGBoost (described later), a method of reducing the calculation cost while maintaining performance is devised.

Regarding XGBoost

The following describes XGBoost that is well-known as a library of the GBDT. In the learning algorithm of XGBoost, two points are devised, that is, reduction of the threshold candidates and treatment of a missing value.

First, the following describes reduction of the threshold candidates. The greedy method described above has a problem such that the calculation cost is high. In XGBoost, the number of threshold candidates is reduced by a method of Weighted Quantile Sketch. In this method, the sum of the gradient information of the sample data branching to the left and the right is important in calculating the branch score (Gain), and only a threshold with which the sum of the gradient information varies at a constant ratio is made to be a candidate to be searched for. Specifically, a second-order gradient h of the sample is used. Assuming that the number of dimensions of the feature amount is f, a set of the feature amount and the second-order gradient h of the sample data is represented by the following expression (20). D _(f)={(X _(1f) ,h ₁),(x _(2f) ,h ₂), . . . ,(x _(nf) ,h _(n))}  (20)

A RANK function r_(f) is defined as represented by the following expression (21).

$\begin{matrix} {{r_{f}(z)} = {\frac{1}{\Sigma_{{({x,h})} \in D_{f}}h}\Sigma_{{{({x,h})} \in D_{f}},{x < z}}h}} & (21) \end{matrix}$

In this case, z is a threshold candidate. The RANK function r_(f) in the expression (21) represents a ratio of the sum of second-order gradients of the sample data smaller than a certain threshold candidate to the sum of second-order gradients of all pieces of sample data. In the end, a set of certain threshold candidates {s_(f1), s_(f2), . . . , s_(fl)} needs to be obtained for a feature amount represented by the dimension f, which is obtained by the following expression (22). |r _(f)(s _(fj))−r _(f)(s _(fj+1))|<ε s _(fl)=min({x _(1f) ,x _(2f) , . . . ,x _(nf)}) s _(fl)=max({x _(1f) ,x _(2f) , . . . ,x _(nf)})  (22)

In this case, ε is a parameter for determining a degree of reduction of the threshold candidates, and about 1/ε threshold candidates can be obtained.

As Weighted Quantile Sketch, two patterns can be considered, that is, a global pattern in which Weighted Quantile Sketch is performed at the first node of the decision tree (collectively performed on all pieces of sample data), and a local pattern in which Weighted Quantile Sketch is performed at each node (performed each time on a sample assigned to a corresponding node). It has been found that the local pattern is appropriate in view of generalization performance, so that the local pattern is employed in XGBoost.

Next, the following describes treatment of a missing value. There is no typically effective method of treating the missing value of sample data to be input in the field of machine learning, irrespective of the GBDT and the decision tree. There are a method of complementing the missing value with an average value, a median, a cooperative filter, or the like, and a method of excluding a feature amount including a large number of missing values, for example, but these methods are successfully implemented in not so many cases in view of performance. However, the structured data often includes a missing value, so that some measure is required in a practical use.

In XGBoost, the learning algorithm is devised to directly treat the sample data including the missing value. This is a method of obtaining a score at the time when all pieces of data of the missing value are assigned to any of the left and the right nodes in obtaining the branch score at the node. In a case of performing Weighted Quantile Sketch described above, the threshold candidate may be obtained for a set excluding the sample data including the missing value.

Regarding LightGBM

Next, the following describes LightGBM as a library of the GBDT. LightGBM employs a fast algorithm employing quantization of the feature amount, what is called binning, for preprocessing, and utilizing a GPU for calculating the branch score. Performance of LightGBM is substantially the same as that of XGBoost, and learning speed of LightGBM is several times higher than that of XGBoost. In recent years, users of LightGBM have been increased.

First, the following describes quantization of the feature amount. When a data set is large-scale, the branch score needs to be calculated for a large number of threshold candidates. In LightGBM, the number of threshold candidates is reduced by quantizing the feature amount as preprocessing of learning. Additionally, due to quantization, values and the number of threshold candidates do not vary for each node as in XGBoost, so that LightGBM is indispensable processing in a case of utilizing the GPU.

Various studies have been carried out for quantization of the feature amount under the name of binning. In LightGBM, the feature amount is divided into k bins, and only k threshold candidates are present. k is 255, 63, and 15, for example, and performance or learning speed varies depending on the data set.

Calculation of the branch score is simplified due to quantization of the feature amount. Specifically, the threshold candidate becomes a simple quantized value. Thus, it is sufficient to create a histogram of a first-order gradient and a second-order gradient for each feature amount, and obtain the branch score for each bin (quantized value). This is called a feature amount histogram.

Next, the following describes calculation of the branch score utilizing the GPU. Calculation patterns of the branch score are 256 at the maximum because the feature amount is quantized, but the number of pieces of sample data may exceed tens of thousands depending on the data set, so that creation of the histogram dominates learning time. As described above, the feature amount histogram needs to be obtained in calculating the branch score. In a case of utilizing the GPU, a plurality of threads need to update the same histogram, but the same bin may be updated at this point. Thus, an Atomic operation needs to be used, and performance is deteriorated when a ratio of updating the same bin is high. Thus, in LightGBM, which of the histograms of the first-order gradient and the second-order gradient is used for updating the value is determined for each thread in creating the histogram, which lowers a frequency of updating the same bin.

Configuration of Learning and Discrimination Device

FIG. 2 is a diagram illustrating an example of a module configuration of the learning and discrimination device according to the embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a pointer memory. FIG. 4 is a diagram illustrating an example of a module configuration of a learning module. The following describes the module configuration of a learning and discrimination device 1 according to the present embodiment with reference to FIG. 2 to FIG. 4 .

As illustrated in FIG. 2 , the learning and discrimination device 1 according to the present embodiment includes a CPU 10, a learning module 20, a data memory 30, a model memory 40, and a classification module 50. Among these, the learning module 20, the data memory 30, the model memory 40, and the classification module 50 are configured by an FPGA. The CPU 10 can perform data communication with the FPGA via a bus. In addition to the components illustrated in FIG. 2 , the learning and discrimination device 1 may include other components such as a RAM serving as a work area of the CPU 10, a read only memory (ROM) storing a computer program and the like executed by the CPU 10, an auxiliary storage device storing various kinds of data (a computer program and the like), and a communication I/F for communicating with an external device, for example.

The CPU 10 is an arithmetic device that controls learning of the GBDT as a whole. The CPU 10 includes a control unit 11. The control unit 11 controls respective modules including the learning module 20, the data memory 30, the model memory 40, and the classification module 50. The control unit 11 is implemented by a computer program executed by the CPU 10.

The learning module 20 is a hardware module that calculates a number of an optimum feature amount (hereinafter, also referred to as a “feature amount number” in some cases) for each node included in a decision tree, and a threshold, and in a case in which the node is a leaf, calculates a leaf weight to be written into the model memory 40. As illustrated in FIG. 4 , the learning module 20 also includes gain calculating modules 21_1, 21_2, . . . , and 21_n (gain calculators) and an optimum condition deriving module 22. In this case, n is a number at least equal to or larger than the number of feature amounts of sample data (including both of learning data and discrimination data). In a case of indicating an optional gain calculating module among the gain calculating modules 21_1, 21_2, . . . , and 21_n, or a case in which the gain calculating modules 21_1, 21_2, . . . , and 21_n are collectively called, they are simply referred to as a “gain calculating module 21”.

The gain calculating module 21 is a module that calculates a branch score at each threshold using the expression (19) described above for a corresponding feature amount among the feature amounts included in the sample data to be input. In this case, the learning data of the sample data includes a label (true value) in addition to the feature amount, and the discrimination data of the sample data includes the feature amount and does not include the label. Each gain calculating module 21 includes a memory that performs an operation on respective histograms of all feature amounts input at a time (in 1 clock) and stores the histograms, and performs an operation on all of the feature amounts in parallel. Based on results of the histograms, gains of the respective feature amounts are calculated in parallel. Due to this, processing can be performed on all of the feature amounts at a time, or at the same time, so that speed of learning processing can be significantly improved. Such a method of reading out and processing all of the feature amounts in parallel is called Feature Parallel. To implement this method, a data memory needs to be able to read out all of the feature amounts at a time (in 1 clock). Thus, this method cannot be implemented with a memory having a normal data width such as 32-bit or 256-bit width. With software, the number of bits of data that can be treated by the CPU at a time is typically 64 bits at the maximum, and even when the number of the feature amounts is 100 and the number of bits of each feature amount is 8 bits, 8000 bits are required, so that the method cannot be implemented at all. Thus, in the related art, employed is a method of storing a different feature amount for each address of the memory (for example, 64-bit width that can be treated by the CPU), and storing the feature amounts as a whole across a plurality of addresses. On the other hand, the present method includes novel technical content such that all of the feature amounts are stored at one address of the memory, and all of the feature amounts are read out by one access.

As described above, in the GBDT, learning of the decision tree cannot be parallelized. Thus, how quickly each decision tree is learned dominates the speed of learning processing. On the other hand, in the RF for performing ensemble learning, there is no dependence between the decision trees at the time of learning, so that the learning processing for each decision tree can be easily parallelized, but accuracy thereof is typically lower than that of the GBDT. As described above, by applying Feature Parallel as described above to learning of the GBDT having higher accuracy than that of the RF, speed of the learning processing of the decision tree can be improved.

The gain calculating module 21 outputs the calculated branch score to the optimum condition deriving module 22.

The optimum condition deriving module 22 is a module that receives an input of each branch score corresponding to the feature amount output from each gain calculating module 21, and derives a threshold and a number of the feature amount (feature amount number) the branch score of which is the largest. The optimum condition deriving module 22 writes the derived feature amount number and threshold into the model memory 40 as branch condition data of a corresponding node (an example of data of a node).

The data memory 30 is an SRAM that stores various kinds of data. The data memory 30 includes a pointer memory 31, a feature memory 32, and a state memory 33.

The pointer memory 31 is a memory that stores a storage destination address of the sample data stored in the feature memory 32. As illustrated in FIG. 3 , the pointer memory 31 includes a bank A (bank region) and a bank B (bank region). An operation of dividing a region into two banks including the bank A and the bank B, and storing the storage destination address of the sample data will be described later in detail with reference to FIG. 5 to FIG. 13 . The pointer memory 31 may have three or more banks.

The feature memory 32 is a memory that stores the sample data (including the learning data and the discrimination data).

The state memory 33 is a memory that stores the state information (w, g, and h described above) and label information.

The model memory 40 is an SRAM that stores branch condition data (the feature amount number and the threshold) for each node of the decision tree, a leaf flag (flag information, an example of data of the node) indicating whether the node is a leaf, and a leaf weight in a case in which the node is a leaf.

The classification module 50 is a hardware module that distributes pieces of sample data for each node and each decision tree. The classification module 50 calculates the state information (w, g, h) to be written into the state memory 33.

Not only in discrimination (branching) of the sample data (learning data) in the learning processing described above but also in discrimination processing for the sample data (discrimination data), the classification module 50 can discriminate the discrimination data with the same module configuration. At the time of discrimination processing, processing performed by the classification module 50 can be pipelined by collectively reading all of the feature amounts, and the processing speed can be increased such that one piece of sample data is discriminated for each clock. On the other hand, in a case in which the feature amounts cannot be collectively read as described above, which of the feature amounts is required cannot be found unless branching into the respective node, so that the processing cannot be pipelined in a form of accessing an address of a corresponding feature amount each time.

Assuming that a plurality of classification modules 50 described above are provided, a plurality of pieces of discrimination data may be divided (Data Parallel) to be distributed to the respective classification modules 50, and each of the classification modules 50 may be made to perform discrimination processing to increase the speed of discrimination processing.

Learning Processing of Learning and Discrimination Device

The following specifically describes learning processing of the learning and discrimination device 1 with reference to FIG. 5 to FIG. 13 .

Initialization

FIG. 5 is a diagram illustrating an operation of a module at the time of initializing the learning and discrimination device according to the embodiment. As illustrated in FIG. 5 , first, the control unit 11 initializes the pointer memory 31. For example, as illustrated in FIG. 5 , the control unit 11 writes, into the bank A of the pointer memory 31, addresses of the pieces of sample data (learning data) in the feature memory 32 corresponding to the number of pieces of learning data in order (for example, in ascending order of the address).

All pieces of the learning data are not necessarily used (all addresses are not necessarily written), and it may be possible to use pieces of the learning data that are randomly selected (write addresses of the selected pieces of the learning data) based on a probability corresponding to a predetermined random number by what is called data subsampling. For example, in a case in which a result of data subsampling is 0.5, half of all addresses of the pieces of the learning data may be written into the pointer memory 31 (in this case, the bank A) with a half probability corresponding to the random number. To generate a random number, a pseudorandom number created by a Linear Feedback Shift Register (LFSR) can be used.

All of the feature amounts of the pieces of learning data used for learning are not necessarily used, and it may be possible to use only feature amounts that are randomly selected (for example, selected half thereof) based on a probability corresponding to the random number similarly to the above description by what is called feature subsampling. In this case, for example, as data of feature amounts other than the feature amounts selected by feature subsampling, constants may be output from the feature memory 32. Due to this, an effect is exhibited such that generalization performance for unknown data (discrimination data) is improved.

Determination of Branch Condition Data at Depth 0, Node 0

FIG. 6 is a diagram illustrating an operation of a module in a case of determining node parameters at depth 0, node 0 of the learning and discrimination device according to the embodiment. It is assumed that the top of a hierarchy of the decision tree is “depth 0”, hierarchical levels lower than the top are referred to as “depth 1”, “depth 2”, . . . in order, the leftmost node at a specific hierarchical level is referred to as “node 0”, and nodes on the right side thereof are referred to as “node 1”, “node 2”, . . . in order.

As illustrated in FIG. 6 , first, the control unit 11 transmits a start address and an end address to the learning module 20, and causes the learning module 20 to start processing by a trigger. The learning module 20 designates an address of a target piece of the learning data from the pointer memory 31 (bank A) based on the start address and the end address, reads out the learning data (feature amount) from the feature memory 32, and reads out the state information (w, g, h) from the state memory 33 based on the address.

In this case, as described above, each gain calculating module 21 of the learning module 20 calculates a histogram of a corresponding feature amount, stores the histogram in the SRAM thereof, and calculates a branch score at each threshold based on a result of the histogram. The optimum condition deriving module 22 of the learning module 20 receives an input of the branch score corresponding to each feature amount output from the gain calculating module 21, and derives a threshold and a number of the feature amount (feature amount number) the branch score of which is the largest. The optimum condition deriving module 22 then writes the derived feature amount number and threshold into the model memory 40 as branch condition data of the corresponding node (depth 0, node 0). At this point, the optimum condition deriving module 22 sets the leaf flag to be “0” to indicate that branching is further performed from the node (depth 0, node 0), and writes the data of the node (this may be part of the branch condition data) into the model memory 40.

The learning module 20 performs the operation described above by designating the addresses of the pieces of learning data written into the bank A in order, and reading out the respective pieces of learning data from the feature memory 32 based on the addresses.

Data Branch Processing at Depth 0, Node 0

FIG. 7 is a diagram illustrating an operation of a module at the time of branching at depth 0, node 0 of the learning and discrimination device according to the embodiment.

As illustrated in FIG. 7 , the control unit 11 transmits the start address and the end address to the classification module 50, and causes the classification module 50 to start processing by a trigger. The classification module 50 designates the address of the target learning data from the pointer memory 31 (bank A) based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 also reads out the branch condition data (the feature amount number, the threshold) of the corresponding node (depth 0, node 0) from the model memory 40. The classification module 50 determines whether to cause the read-out sample data to branch to the left side or to the right side of the node (depth 0, node 0) in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the other bank (writing bank) (in this case, the bank B) (a bank region for writing) different from a read-out bank (in this case, the bank A) (a bank region for reading-out) of the pointer memory 31.

At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address in the bank B as illustrated in FIG. 7 . If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address in the bank B. Due to this, in the writing bank (bank B), the address of the learning data branched to the left side of the node is written as a lower address, and the address of the learning data branched to the right side of the node is written as a higher address, in a clearly separated manner. Alternatively, in the writing bank, the address of the learning data branched to the left side of the node may be written as a higher address, and the address of the learning data branched to the right side of the node may be written as a lower address, in a separated manner.

In this way, the two banks, that is, the bank A and the bank B are configured in the pointer memory 31 as described above, and the memory can be efficiently used by alternately performing reading and writing thereon although the capacity of the SRAM in the FPGA is limited. As a simplified method, there is a method of configuring each of the feature memory 32 and the state memory 33 to have two banks. However, the data indicating the address in the feature memory 32 is typically smaller than the sample data, so that usage of the memory can be further reduced by a method of preparing the pointer memory 31 to indirectly designate the address as in the present embodiment.

As the operation described above, the classification module 50 performs branch processing on all pieces of the learning data. However, after the branch processing ends, the respective numbers of pieces of learning data separated to the left side and the right side of the node (depth 0, node 0) are not the same, so that the classification module 50 returns, to the control unit 11, an address (intermediate address) in the writing bank (bank B) corresponding to a boundary between the addresses of the learning data branched to the left side and the addresses of the learning data branched to the right side. The intermediate address is used in the next branch processing.

Determination of Branch Condition Data at Depth 1, Node 0

FIG. 8 is a diagram illustrating an operation of a module in a case of determining node parameters at depth 1, node 0 of the learning and discrimination device according to the embodiment. The operation is basically the same as that in the processing of determining the branch condition data at depth 0, node 0 illustrated in FIG. 6 , but the hierarchical level of a target node is changed (from depth 0 to depth 1), so that roles of the bank A and the bank B in the pointer memory 31 are reversed. Specifically, the bank B serves as the read-out bank, and the bank A serves as the writing bank (refer to FIG. 9 ).

As illustrated in FIG. 8 , the control unit 11 transmits the start address and the end address to the learning module 20 based on the intermediate address received from the classification module 50 through the processing at depth 0, and causes the learning module 20 to start processing by a trigger. The learning module 20 designates the address of the target learning data from the pointer memory 31 (bank B) based on the start address and the end address, reads out the learning data (feature amount) from the feature memory 32 based on the address, and reads out the state information (w, g, h) from the state memory 33. Specifically, as illustrated in FIG. 8 , the learning module 20 designates the addresses in order from the left side (lower address) to the intermediate address in the bank B.

In this case, as described above, each gain calculating module 21 of the learning module 20 stores the feature amount of the read-out learning data in the SRAM thereof, and calculates the branch score at each threshold. The optimum condition deriving module 22 of the learning module 20 receives an input of the branch score corresponding to each feature amount output from the gain calculating module 21, and derives a threshold and a number of the feature amount (feature amount number) the branch score of which is the largest. The optimum condition deriving module 22 then writes the derived feature amount number and threshold into the model memory 40 as the branch condition data of the corresponding node (depth 1, node 0). At this point, the optimum condition deriving module 22 sets the leaf flag to be “0” to indicate that branching is further performed from the node (depth 1, node 0), and writes the data of the node (this may be part of the branch condition data) into the model memory 40.

The learning module 20 performs the operation described above by designating the addresses in order from the left side (lower address) to the intermediate address in the bank B, and reading out each piece of the learning data from the feature memory 32 based on the addresses.

Data Branch Processing at Depth 1, Node 0

FIG. 9 is a diagram illustrating an operation of a module at the time of branching at depth 1, node 0 of the learning and discrimination device according to the embodiment.

As illustrated in FIG. 9 , the control unit 11 transmits the start address and the end address to the classification module 50 based on the intermediate address received from the classification module 50 through the processing at depth 0, and causes the classification module 50 to start processing by a trigger. The classification module 50 designates the address of the target learning data from the left side of the pointer memory 31 (bank B) based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 also reads out the branch condition data (the feature amount number, the threshold) of the corresponding node (depth 1, node 0) from the model memory 40. The classification module 50 determines whether to cause the read-out sample data to branch to the left side or to the right side of the node (depth 1, node 0) in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the other bank (writing bank) (in this case, the bank A) (the bank region for writing) different from the read-out bank (in this case, the bank B) (the bank region for reading-out) of the pointer memory 31.

At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address (from the received start address) in the bank A as illustrated in FIG. 9 . If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address (from the received end address, that is, the previous intermediate address) in the bank A. Due to this, in the writing bank (bank A), the address of the learning data branched to the left side of the node is written as a lower address, and the address of the learning data branched to the right side of the node is written as a higher address, in a clearly separated manner. Alternatively, in the writing bank, the address of the learning data branched to the left side of the node may be written as a higher address, and the address of the learning data branched to the right side of the node may be written as a lower address, in a separated manner.

As the operation described above, the classification module 50 performs branch processing on a piece of learning data designated by the address written on the left side of the intermediate address in the bank B among all the pieces of learning data. However, after the branch processing ends, the respective numbers of pieces of learning data separated to the left side and the right side of the node (depth 1, node 0) are not the same, so that the classification module 50 returns, to the control unit 11, an address (intermediate address) in the writing bank (bank A) corresponding to the middle of the addresses of the learning data branched to the left side and the addresses of the learning data branched to the right side. The intermediate address is used in the next branch processing.

Determination of Branch Condition Data at Depth 1, Node 1

FIG. 10 is a diagram illustrating an operation of a module in a case of determining node parameters at depth 1, node 1 of the learning and discrimination device according to the embodiment. Similarly to the case of FIG. 8 , the hierarchical level is the same as that of the node at depth 1, node 0, so that the bank B serves as the read-out bank, and the bank A serves as the writing bank (refer to FIG. 11 ).

As illustrated in FIG. 10 , the control unit 11 transmits the start address and the end address to the learning module 20 based on the intermediate address received from the classification module 50 through the processing at depth 0, and causes the learning module 20 to start processing by a trigger. The learning module 20 designates the address of the target learning data from the pointer memory 31 (bank B) based on the start address and the end address, reads out the learning data (feature amount) from the feature memory 32 based on the address, and reads out the state information (w, g, h) from the state memory 33. Specifically, as illustrated in FIG. 10 , the learning module 20 designates the addresses in order from the right side (higher address) to the intermediate address in the bank B.

In this case, as described above, each gain calculating module 21 of the learning module 20 stores each feature amount of the read-out learning data in the SRAM thereof, and calculates the branch score at each threshold. The optimum condition deriving module 22 of the learning module 20 receives an input of the branch score corresponding to each feature amount output from the gain calculating module 21, and derives a threshold and a number of the feature amount (feature amount number) the branch score of which is the largest. The optimum condition deriving module 22 then writes the derived feature amount number and threshold into the model memory 40 as the branch condition data of the corresponding node (depth 1, node 1). At this point, the optimum condition deriving module 22 sets the leaf flag to be “0” to indicate that branching is further performed from the node (depth 1, node 1), and writes the data of the node (this may be part of the branch condition data) into the model memory 40.

The learning module 20 performs the operation described above by designating the addresses in order from the right side (higher address) to the intermediate address in the bank B, and reading out each piece of the learning data from the feature memory 32 based on the addresses.

Data Branch Processing at Depth 1, Node 1

FIG. 11 is a diagram illustrating an operation of a module at the time of branching at depth 1, node 1 of the learning and discrimination device according to the embodiment.

As illustrated in FIG. 11 , the control unit 11 transmits the start address and the end address to the classification module 50 based on the intermediate address received from the classification module 50 through the processing at depth 0, and causes the classification module 50 to start processing by a trigger. The classification module 50 designates the address of the target learning data from the right side of the pointer memory 31 (bank B) based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 reads out the branch condition data (the feature amount number, the threshold) of the corresponding node (depth 1, node 1) from the model memory 40. The classification module 50 then determines whether to cause the read-out sample data to branch to the left side or to the right side of the node (depth 1, node 1) in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the other bank (writing bank) (in this case, the bank A) (the bank region for writing) different from the read-out bank (in this case, the bank B) (the bank region for reading-out) of the pointer memory 31.

At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address (from the received start address, that is, the previous intermediate address) in the bank A as illustrated in FIG. 11 . If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address (from the received end address) in the bank A. Due to this, in the writing bank (bank A), the address of the learning data branched to the left side of the node is written as a lower address, and the address of the learning data branched to the right side of the node is written as a higher address, in a clearly separated manner. Alternatively, in the writing bank, the address of the learning data branched to the left side of the node may be written as a higher address, and the address of the learning data branched to the right side of the node may be written as a lower address, in a separated manner. In such a case, the operation in FIG. 9 is required to be performed at the same time.

As the operation described above, the classification module 50 performs branch processing on a piece of learning data designated by the address written on the right side of the intermediate address in the bank B among all the pieces of learning data. However, after the branch processing ends, the respective numbers of pieces of learning data separated to the left side and the right side of the node (depth 1, node 1) are not the same, so that the classification module 50 returns, to the control unit 11, an address (intermediate address) in the writing bank (bank A) corresponding to the middle of the addresses of the learning data branched to the left side and the addresses of the learning data branched to the right side. The intermediate address is used in the next branch processing.

Case in which Branching is not Performed at Time of Determining Branch Condition Data at Depth 1, Node 1

FIG. 12 is a diagram illustrating an operation of a module in a case in which branching is not performed as a result of determining node parameters at depth 1, node 1 of the learning and discrimination device according to the embodiment. Similarly to the case of FIG. 8 , the hierarchical level is the same as that of the node at depth 1, node 0, so that the bank B serves as the read-out bank.

As illustrated in FIG. 12 , the control unit 11 transmits the start address and the end address to the learning module 20 based on the intermediate address received from the classification module 50 through the processing at depth 0, and causes the learning module 20 to start processing by a trigger. The learning module 20 designates the address of the target learning data from the pointer memory 31 (bank B) based on the start address and the end address, reads out the learning data (feature amount) from the feature memory 32 based on the address, and reads out the state information (w, g, h) from the state memory 33. Specifically, as illustrated in FIG. 12 , the learning module 20 designates the addresses in order from the right side (higher address) to the intermediate address in the bank B.

If it is determined that branching will not be further performed from the node (depth 1, node 1) based on the calculated branch score and the like, the learning module 20 sets the leaf flag to be “1”, writes the data of the node (this may be part of the branch condition data) into the model memory 40, and transmits, to the control unit 11, the fact that the leaf flag of the node is “1”. Due to this, it is recognized that branching is not performed to a lower hierarchical level than the node (depth 1, node 1). In a case in which the leaf flag of the node (depth 1, node 1) is “1”, the learning module 20 writes a leaf weight (w) (this may be part of the branch condition data) into the model memory 40 in place of the feature amount number and the threshold. Due to this, the capacity of the model memory 40 can be reduced as compared with a case where capacities are secured in the model memory 40 separately.

By advancing the above processing illustrated in FIG. 6 to FIG. 12 for each hierarchical level (depth), the entire decision tree is completed (the decision tree is learned).

Case in which Learning of Decision Tree is Completed

FIG. 13 is a diagram illustrating an operation of a module at the time of updating the state information of all pieces of sample data in a case in which learning of the decision tree is completed by the learning and discrimination device according to the embodiment.

In a case in which learning of one decision tree included in the GBDT is completed, a first-order gradient g and a second-order gradient h corresponding to the error function of each piece of the learning data, and the leaf weight w for each piece of the learning data need to be calculated for being used in boosting (in this case, gradient boosting) to the next decision tree. As illustrated in FIG. 13 , the control unit 11 causes the classification module 50 to start calculation described above by a trigger. The classification module 50 performs processing of branch determination for nodes at all depths (hierarchical levels) on all pieces of the learning data, and calculates the leaf weight corresponding to each piece of the learning data. The classification module 50 then calculates the state information (w, g, h) for the calculated leaf weight based on the label information, and writes the state information (w, g, h) back to an original address of the state memory 33. In this way, learning of the next decision tree is performed by utilizing updated state information.

As described above, in the learning and discrimination device 1 according to the present embodiment, the learning module 20 includes memories (for example, SRAMs) for reading respective feature amounts of the input sample data. Due to this, all of the feature amounts of the sample data can be read out by one access, and each gain calculating module 21 can perform processing on all of the feature amounts at a time, so that speed of learning processing for the decision tree can be significantly improved.

In the learning and discrimination device 1 according to the present embodiment, the two banks, that is, the bank A and the bank B are configured in the pointer memory 31, and reading and writing are alternately performed. Due to this, the memory can be efficiently used. As a simplified method, there is a method of configuring each of the feature memory 32 and the state memory 33 to have two banks. However, the data indicating the address in the feature memory 32 is typically smaller than the sample data, so that the memory capacity can be further saved by a method of preparing the pointer memory 31 to indirectly designate the address as in the present embodiment. If it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in order from a lower address in the writing bank of the two banks, and if it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in order from a higher address in the writing bank. Due to this, in the writing bank, the address of the learning data branched to the left side of the node is written as a lower address, and the address of the learning data branched to the right side of the node is written as a higher address, in a clearly separated manner.

Modification

FIG. 14 is a diagram illustrating an example of a configuration of the model memory of the learning and discrimination device according to a modification. With reference to FIG. 14 , the following describes a configuration in which the memory is provided for each depth (hierarchical level) of the decision tree in the model memory 40 of the learning and discrimination device 1 according to the present modification.

As illustrated in FIG. 14 , the model memory 40 of the learning and discrimination device 1 according to the present modification includes a memory 41_1 for depth 0, memory 41_2 for depth 1, . . . , and a memory 41_m for depth (m−1) for storing the data (specifically, the branch condition data) for each depth (hierarchical level) of the model data of the learned decision tree. In this case, m is a number at least equal to or larger than a number of the depth (hierarchical level) of the model of the decision tree. That is, the model memory 40 includes an independent port for extracting data (depth 0 node data, depth 1 node data, . . . , depth (m−1) node data) at the same time for each depth (hierarchical level) of the model data of the learned decision tree. Due to this, the classification module 50 can read out the data (branch condition data) corresponding to the next node at all depths (hierarchical levels) in parallel based on a branch result at the first node of the decision tree, and can perform branch processing at the respective depths (hierarchical levels) at the same time in 1 clock (pipeline processing) on a piece of the sample data (discrimination data) without using a memory. Due to this, discrimination processing performed by the classification module 50 takes only time corresponding to the number of pieces of sample data, and speed of discrimination processing can be significantly improved. On the other hand, in the related art, the sample data is copied to a new memory region for each node, which affects the speed due to time for reading and writing performed by the memory, and the time required for discrimination processing is equal to (the number of pieces of sample data×the number of the depth (hierarchical level)), so that the discrimination processing according to the present modification has a great advantage as described above.

FIG. 15 is a diagram illustrating an example of a configuration of the classification module of the learning and discrimination device according to the modification. As illustrated in FIG. 15 , the classification module 50 includes a node 0 discriminator 51_1, a node 1 discriminator 51_2, a node 2 discriminator 51_3, . . . . A piece of the sample data for each clock is supplied from the feature memory 32 as a feature amount. As illustrated in FIG. 15 , the feature amount is input to the node 0 discriminator 51_1 first, and the node 0 discriminator 51_1 receives the data of the node (depth 0 node data) (a condition of whether to branch to the right or to the left, and the feature amount number to be used) from the corresponding memory 41_1 for depth 0 of the model memory 40. The node 0 discriminator 51_1 discriminates whether the corresponding sample data branches to the right or to the left in accordance with the condition. In this case, the latency of each memory for depth (the memory 41_1 for depth 0, the memory 41_2 for depth 1, a memory 41_3 for depth 2, . . . ) is assumed to be 1 clock. Based on the result obtained by the node 0 discriminator 51_1, whether the sample data branches to what number of node is designated by an address in the next memory 41_2 for depth 1, and the data of the corresponding node (depth 1 node data) is extracted and input to the node 1 discriminator 51_2.

The latency of the memory 41_1 for depth 0 is 1 clock, so that the feature amount is similarly input to the node 1 discriminator 51_2 with a delay of 1 clock. The feature amount of the next sample data is input to the node 0 discriminator 51_1 with the same clock. In this way, by performing discrimination through the pipeline processing, one decision tree as a whole can discriminate one piece of sample data with 1 clock on the precondition that the memories perform output at the same time for each depth. Only one address is required for the memory 41_1 for depth 0 because there is one node at depth 0, two addresses are required for the memory 41_2 for depth 1 because there are two nodes at depth 1, similarly, four addresses are required for the memory 41_3 for depth 2, and eight addresses are required for a memory for depth 3 (not illustrated). Although the classification module 50 discriminates the entire tree, learning may be performed using only the node 0 discriminator 51_1 at the time of learning the node to reduce a circuit scale by using the same circuit.

Second Embodiment

The following describes the learning and discrimination device according to a second embodiment, mainly about differences from the learning and discrimination device 1 according to the first embodiment. The first embodiment describes the learning processing and the discrimination processing by the GBDT assuming that there is one data memory 30 in which the sample data is stored. The present embodiment describes an operation of performing learning processing by dividing the data memory into a plurality of parts to implement Data Parallel for processing a plurality of pieces of sample data in parallel.

Regarding Data Parallel

FIG. 16 is a diagram illustrating an example of a module configuration of the learning and discrimination device to which Data Parallel is applied. With reference to FIG. 16 , the following describes a configuration of a learning and discrimination device 1 a as an example of a configuration for implementing Data Parallel.

To implement Data Parallel for the sample data (the learning data or the discrimination data), first, the data memory may be divided into two data memories 30 a and 30 b to hold divided pieces of sample data as illustrated in FIG. 16 . Although not illustrated in the data memory 30 b of FIG. 16 , the data memory 30 b also includes the pointer memory 31, the feature memory 32, and the state memory 33 similarly to the data memory 30 a. However, it is not sufficient to simply dividing the memory that holds the sample data, and a mechanism for performing processing (learning processing, discrimination processing, and the like) on the divided pieces of sample data in parallel is required. In the configuration example illustrated in FIG. 16 , the number of arranged modules that perform discrimination processing is the same as that of the divided data memories. That is, the learning and discrimination device 1 a includes classification modules 50 a and 50 b for performing discrimination processing on respective pieces of sample data stored in the two data memories 30 a and 30 b in parallel. Focusing on each individual module, assuming that processing is performed by Feature Parallel, the configuration of the module is changed little for implementing Data Parallel as described above, so that implementation thereof is facilitated.

Data parallel for increasing speed of learning processing, that is, processing performed by the learning module 20 has a problem such that the circuit scale is increased because the data memory is divided into the two data memories 30 a and 30 b for holding divided pieces of sample data, and the memory that holds the histogram (hereinafter, also referred to as a “gradient histogram” in some cases) of the feature amount calculated in a process of the learning processing and the gradient information (refer to the expression (11) described above) is increased in proportion to the number of division of the data memory as described above.

Method of Calculating Branch Score Using Gradient Histogram

First, the following describes a method of calculating the branch score by the learning module 20. In this case, the feature amount of the sample data (in this case, the learning data) is assumed to be quantized to have a certain bit width. For example, in a case in which the feature amount is 8 bits (values of 256 patterns) and the number of dimensions of the feature amount is 100, the learning module 20 calculates branch scores of 256×100=25600 patterns. In this case, the number of candidates of the threshold is 256.

To calculate the branch score corresponding to a certain branch condition (one threshold corresponding to one feature amount), it is required to obtain the sum of the gradient information of the learning data having the feature amount equal to or larger than the threshold (corresponding to G_(R) and H_(R) in the expression (19) described above), and the sum of the gradient information of the learning data having the feature amount smaller than the threshold (corresponding to G_(L) and H_(L) in the expression (19) described above) from the learning data at the present node. In this case, as represented by the following (Table 1), the following specifically describes a case in which the number of pieces of the learning data is 4, the number of dimensions of the feature amount is 1 and values thereof are 3 patterns, and the gradient information is the first-order gradient g.

TABLE 1 Sample data number Feature amount g 1 0 0.1 2 1 0.2 3 1 0.1 4 2 −0.3

As represented by (Table 1), there are 3 patterns of feature amounts, that is, 0, 1, and 2, so that thresholds are also 0, 1, and 2, the sum of the gradient information at each threshold is a value represented by the following (Table 2), and the branch score corresponding to each of the thresholds of 3 patterns is calculated.

TABLE 2 Threshold G_(L) G_(R) 0 0 0.1 + 0.2 + 0.1 − 0.3 = 0.1 1 0.1 0.2 + 0.1 − 0.3 = 0 2 0.1 + 0.2 + 0.1 = 0.4 −0.3

To obtain the sum of the gradient information for a specific threshold, it is required to refer to all pieces of the learning data at the present node. If this processing should be performed for all thresholds every time, it takes very long processing time. For example, in a case in which the feature amount is 8 bits (256 patterns), there are also 256 patterns of thresholds, so that the sum of the gradient information needs to be obtained (the number of pieces of learning data at the present node×256) times. It takes very long processing time, so that calculation processing of the branch score is simplified by obtaining the sum of the gradient information for each value of the feature amount (gradient histogram) and the sum total of the gradient information in advance, and taking a cumulative sum of the gradient histogram.

In a case of the sample data represented by (Table 1) described above, the sum of the gradient information for each value of the feature amount (gradient histogram) becomes a value represented by the following (Table 3).

TABLE 3 Feature amount Gradient histogram 0 0.1 1 0.2 + 0.1 = 0.3 2 −0.3

The sum total of the gradient information for each value of the feature amount is 0.1+0.2+0.1−0.3=0.1. In this case, the sum G_(L) of the gradient information is obtained by obtaining the cumulative sum of the gradient histogram, G_(R) of the gradient information is obtained by subtracting the sum G_(L) of the gradient information from the sum total of the gradient information, and the sums G_(L) and G_(R) of the gradient information for each threshold becomes values represented by the following (Table 4).

TABLE 4 G_(L) (Cumulative sum of G_(R) Threshold gradient histogram) (Sum total - G_(L)) 0 0 0.1 1 0.1 0 2 0.1 + 0.3 = 0.4 −0.3

With this method, it is sufficient to refer to the learning data at the present node per one time, and thereafter, the branch scores for all branch conditions can be obtained by referring to gradient histograms corresponding to the number of thresholds. In a case in which the feature amount is 8 bits (256 patterns), it is sufficient to perform processing (the number of pieces of learning data at the present node+256) times. The above case is a case in which the feature amount has one dimension, but even when the feature amount has two or more dimensions, the same processing can be calculated in parallel by obtaining the gradient histogram for each dimension of the feature amount. The following describes a configuration and an operation for calculating the gradient histogram and obtaining the branch condition data by the learning module 20 illustrated in FIG. 17 the configuration of which is illustrated in more detail based on FIG. 4 illustrating the configuration of the learning module 20 that performs learning by Feature Parallel in the first embodiment, and further describes a configuration and an operation in a case of using a Data Parallel configuration.

Configuration Example of Learning Module for Obtaining Branch Condition Data Using Gradient Histogram

FIG. 17 is a diagram illustrating an example of a specific module configuration of the learning module. With reference to FIG. 17 , the following describes a configuration and an operation of the learning module 20 representing the configuration illustrated in FIG. 4 described above in more detail.

The learning module 20 illustrated in FIG. 17 includes the gain calculating modules 21_1, 21_2, . . . , and 21_n, and the optimum condition deriving module 22. In this case, n is a number at least equal to or larger than the number of types of the feature amounts of the sample data (in this case, the learning data). In a case of indicating an optional gain calculating module among the gain calculating modules 21_1, 21_2, . . . , and 21_n, or a case in which the gain calculating modules 21_1, 21_2, . . . , and 21_n are collectively called, they are simply referred to as the “gain calculating module 21”.

Each of the gain calculating modules 21_1 to 21_1 n is a module that calculates the branch score at each threshold using the expression (19) described above for a corresponding feature amount among the feature amounts included in the sample data to be input. The gain calculating module 21_1 includes a gradient histogram calculating module 61_1, an accumulated gradient calculating module 62_1, and a calculating module 63_1.

The gradient histogram calculating module 61_1 is a module that calculates, using each value of the feature amount of the input sample data as a bin of the histogram, the gradient histogram by integrating values of the gradient information corresponding to the sample data.

The accumulated gradient calculating module 62_1 is a module that calculates the sums of the gradient information (G_(L), G_(R), H_(L), H_(R)) by obtaining the cumulative sum of the gradient histogram for each threshold of the feature amount.

The calculating module 63_1 is a module that calculates the branch score at each threshold using the expression (19) described above and using the sum of the gradient information calculated by the accumulated gradient calculating module 62_1.

Similarly, the gain calculating module 21_2 includes a gradient histogram calculating module 61_2, an accumulated gradient calculating module 62_2, and a calculating module 63_2, and the same applies to the gain calculating module 21_n. In a case of indicating an optional gradient histogram calculating module among the gradient histogram calculating modules 61_1, 61_2, . . . , and 61_n, or a case in which the gradient histogram calculating modules 61_1, 61_2, . . . , and 61_n are collectively called, they are simply referred to as a “gradient histogram calculating module 61”. In a case of indicating an optional accumulated gradient calculating module among the accumulated gradient calculating modules 62_1, 62_2, . . . , and 62_n, or a case in which the accumulated gradient calculating modules 62_1, 62_2, . . . , and 62_n are collectively called, they are simply referred to as an “accumulated gradient calculating module 62”. In a case of indicating an optional calculating module among the calculating modules 63_1, 63_2, . . . , and 63_n, or a case in which the calculating modules 63_1, 63_2, . . . , and 63_n are collectively called, they are simply referred to as a “calculating module 63”.

The optimum condition deriving module 22 is a module that receives an input of the branch score corresponding to each threshold and each feature amount output from the respective gain calculating modules 21, and derives a threshold and a number of the feature amount (feature amount number) the branch score of which is the largest. The optimum condition deriving module 22 writes the derived feature amount number and threshold into the model memory 40 as the branch condition data (an example of data of the node) of a corresponding node.

Configuration and Operation of Gradient Histogram Calculating Module

FIG. 18 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module of the learning module. With reference to FIG. 18 , the following describes a configuration and an operation of the gradient histogram calculating module 61 in the learning module 20. FIG. 18 illustrates a case in which the feature amount is assumed to have one dimension, and the gradient information is assumed to include the first-order gradient g and the second-order gradient h, which may be simply referred to as gradient information g and gradient information h in some cases.

As illustrated in FIG. 18 , the gradient histogram calculating module 61 includes a data counter 201, an adder 202, a delay 203, a gradient histogram memory 204, a sum total storing memory 205, an adder 206, a delay 207, a gradient histogram memory 208, and a sum total storing memory 209.

The data counter 201 outputs an address for reading out, from the data memory 30, the sample data (feature amount) to be subjected to learning processing and corresponding pieces of gradient information g and h.

The adder 202 adds added gradient information g read out from the gradient histogram memory 204 to the gradient information g that is newly read out from the data memory 30.

The delay 203 outputs the feature amount read out from the data memory 30 with delay to be matched with a timing of writing the gradient information g added by the adder 202 into the gradient histogram memory 204.

The gradient histogram memory 204 is a memory that successively stores the added gradient information g using the value of the feature amount as an address, and stores the gradient histogram for each value (bin) of the feature amount in the end.

The sum total storing memory 205 is a memory that stores the sum total of the gradient information g read out from the data memory 30.

The adder 206 adds the added gradient information h read out from the gradient histogram memory 208 to the gradient information h that is newly read out from the data memory 30.

The delay 207 outputs the feature amount read out from the data memory 30 with delay to be matched with a timing of writing the gradient information h added by the adder 206 into the gradient histogram memory 208.

The gradient histogram memory 208 is a memory that successively stores the added gradient information h using the value of the feature amount as an address, and stores the gradient histogram for each value (bin) of the feature amount in the end.

The sum total storing memory 209 is a memory that stores the sum total of the gradient information h read out from the data memory 30.

The following simply describes an operation procedure of calculating the gradient histogram of the gradient histogram calculating module 61. First, the gradient histogram calculating module 61 reads out a piece of learning data (the feature amount, the gradient information) of the present node stored in the data memory 30 using an address output from the data counter 201. The adder 202 reads out the gradient information g (added gradient information g) from the gradient histogram memory 204 using the feature amount read out from the data memory 30 as an address. The adder 202 then adds the gradient information g (added gradient information g) read out from the gradient histogram memory 204 to the gradient information g read out from the data memory 30, and writes (updates) the added gradient information g into the gradient histogram memory 204 using the feature amount read out from the data memory 30 as an address. The sum total storing memory 205 adds up pieces of the gradient information g each time the gradient information g is read out from the data memory 30, and stores the sum total of the gradient information g. The same applies to processing on the gradient information h performed by the adder 206, the delay 207, the gradient histogram memory 208, and the sum total storing memory 209. The above operation is repeatedly performed on all the pieces of learning data at the present node.

Configuration and Operation of Accumulated Gradient Calculating Module

FIG. 19 is a diagram illustrating an example of a module configuration of the accumulated gradient calculating module of the learning module. With reference to FIG. 19 , the following describes a configuration and an operation of the accumulated gradient calculating module 62 in the learning module 20. FIG. 19 illustrates a case in which the feature amount is assumed to have one dimension, and the gradient information is assumed to include the first-order gradient g and the second-order gradient h.

As illustrated in FIG. 19 , the accumulated gradient calculating module 62 includes a threshold counter 210, an accumulator 211, a delay 212, a difference calculator 213, an accumulator 214, a delay 215, and a difference calculator 216.

The threshold counter 210 outputs a threshold to be an address for reading out, from the gradient histogram memories 204 and 208, the gradient information (g, h) added for each value of the feature amount, that is, the gradient histogram of each value of the feature amount.

The accumulator 211 reads out, from the gradient histogram memory 204, the gradient histogram of the gradient information g corresponding to the threshold (address) output from the threshold counter 210, further accumulates the gradient histogram on the cumulative sum of the gradient histogram that is presently stored, and hold it as a new cumulative sum of the gradient histogram.

The delay 212 outputs, as the sum G_(L) of the gradient information g, the cumulative sum of the gradient histogram of the gradient information g read out from the accumulator 211 with delay to be matched with a timing at which the sum G_(R) of the gradient information g is output from the difference calculator 213.

The difference calculator 213 calculates the sum G_(R) of the gradient information g by subtracting, from the sum total of the gradient information g read out from the sum total storing memory 205, the cumulative sum of the gradient histogram of the gradient information g (that is, the sum G_(L) of the gradient information g) read out from the accumulator 211.

The accumulator 214 reads out, from the gradient histogram memory 208, the gradient histogram of the gradient information h corresponding to the threshold (address) output from the threshold counter 210, further accumulates the gradient histogram on the cumulative sum of gradient histogram that is presently stored, and hold it as a new cumulative sum of the gradient histogram.

The delay 215 outputs, as the sum H_(L) of the gradient information h, the cumulative sum of the gradient histogram of the gradient information h read out from the accumulator 214 with delay to be matched with a timing at which the sum H_(R) of the gradient information h is output from the difference calculator 216.

The difference calculator 216 calculates the sum H_(R) of the gradient information h by subtracting, from the sum total of the gradient information h read out from the sum total storing memory 209, the cumulative sum of the gradient histogram of the gradient information h (that is, the sum H_(L) of the gradient information h) read out from the accumulator 214.

The following simply describes an operation procedure of calculating the sums (G_(L), G_(R), H_(L), H_(R)) of the gradient information performed by the accumulated gradient calculating module 62. The accumulated gradient calculating module 62 starts calculation processing after the gradient histogram calculating module 61 ends an operation of calculation and storage processing for the gradient histogram of the gradient information. That is, after the gradient histogram calculating module 61 ends the calculation processing, each of the gradient histogram memories 204 and 208 holds the gradient histograms of the pieces of gradient information g and h calculated from all the pieces of learning data at the present node.

First, the accumulated gradient calculating module 62 reads out the gradient histogram of the gradient information g stored in the gradient histogram memory 204 using the threshold as an address output from the threshold counter 210. The accumulator 211 reads out, from the gradient histogram memory 204, the gradient histogram of the gradient information g corresponding to the threshold output from the threshold counter 210, accumulates the gradient histogram on the cumulative sum of the gradient histogram that is presently stored, and hold it as a new cumulative sum of the gradient histogram. The difference calculator 213 calculates the sum G_(R) of the gradient information g by subtracting, from the sum total of the gradient information g read out from the sum total storing memory 205, the cumulative sum of the gradient histogram of the gradient information g (that is, the sum G_(L) of the gradient information g) read out from the accumulator 211, and outputs the sum G_(R) to the calculating module 63. The delay 212 outputs, to the calculating module 63, the cumulative sum of the gradient histogram of the gradient information g (that is, the sum G_(L) of the gradient information g) read out from the accumulator 211 at a timing of output by the difference calculator 213. The same applies to processing on the gradient information h (processing of calculating the sums H_(L) and H_(R) of the gradient information h) performed by the accumulator 214, the delay 215, and the difference calculator 216. The above operation is repeatedly performed on all of the thresholds, and this is implemented when the threshold counter 210 sequentially counts up the thresholds to be output in a round.

Gradient Histogram Calculating Module in Case in which Data Parallel is Implemented

FIG. 20 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module in a case in which Data Parallel is implemented. With reference to FIG. 20 , the following describes a configuration and an operation of the gradient histogram calculating module 61 in a case in which Data Parallel is implemented. FIG. 20 illustrates a case in which the number of division for Data Parallel is assumed to be 2, the feature amount is assumed to have one dimension, and the gradient information is assumed to include only the first-order gradient g.

As illustrated in FIG. 20 , to implement Data Parallel the number of division of which is 2, the data memories 30 a and 30 b as divided memories are configured in place of the data memory 30 illustrated in FIG. 18 , and gradient histogram calculating modules 61 a and 61 b are configured in place of the gradient histogram calculating module 61.

As illustrated in FIG. 20 , the gradient histogram calculating module 61 a includes a data counter 201 a, an adder 202 a, a delay 203 a, a gradient histogram memory 204 a, and a sum total storing memory 205 a. The gradient histogram calculating module 61 b includes a data counter 201 b, an adder 202 b, a delay 203 b, a gradient histogram memory 204 b, and a sum total storing memory 205 b. Functions of the data counters 201 a and 201 b, the adders 202 a and 202 b, the delays 203 a and 203 b, the gradient histogram memories 204 a and 204 b, and the sum total storing memories 205 a and 205 b are the same as the respective functions described above with reference to FIG. 18 .

In a case of simply configuring Data Parallel, as illustrated in FIG. 20 , the number of the gradient histogram calculating modules 61 to be arranged may be the same as the number of division similarly to the data memories 30. In this case, the number of the gradient histogram memories is equal to (the dimensions of the feature amount×the number of division). In the example illustrated in FIG. 20 , the feature amount has one dimension and the number of division is 2, so that the two gradient histogram memories 204 a and 204 b are arranged. Additionally, in a case of considering the respective gradient histogram memories for the first-order gradient g and the second-order gradient h as the gradient information, required total capacity of the gradient histogram memory is equal to (capacity of one memory (the number of bins×bit width)×2 (the first-order gradient g, the second-order gradient h)×the dimensions of the feature amount×the number of division). In a large-scale data set, the number of dimensions of the feature amount may be several hundreds to several thousands in many cases, and a large number of memories are required when the number of division is increased. Accordingly, the capacity of the memories becomes a bottleneck, and a circuit scale is increased. For example, in a case in which the feature amount is 8 bits (256 patterns) and has 2000 dimensions, the gradient information includes two gradients, that is, the first-order gradient g and the second-order gradient h, and the bit width of the gradient histogram is 12 bits, 12 [bits]×256=3072 [bits] is established, so that the memory capacity of one gradient histogram memory is required to satisfy 3072 bit. The memory is typically prepared based on a power of 2, so that, in this case, the memory capacity is 4096 bits (4 kbits). Thus, in a case of one division (no division), the total capacity of the gradient histogram memory is represented as follows. 4 [kbits]×2 (the first-order gradient g, the second-order gradient h)×2000 [dimensions]=16 [Mbits]

That is, the memory capacity of 16 Mbits is required per one division (no division), and in a case of dividing the memory, the memory capacity of (the number of division×16 Mbits) is required.

For example, the following considers a case of a chip called virtex UltrScale+VU9P manufactured by Xilinx Inc. as a high-end FPGA. Circuits that can be used for the gradient histogram memory include a distributed RAM and a block RAM. In VU9P, the distributed RAM is 36.1 Mbits at the maximum, and the block RAM is 75.9 Mbits at the maximum. Thus, two-division is a limit in a case of using the distributed RAM as the gradient histogram memory, and four-division is a limit in a case of using the block RAM. The distributed RAM and the block RAM need to be used for purposes other than a purpose of holding the gradient histogram, so that an upper limit of the number of division is smaller than the number described above. Accordingly, in a case in which the set of the feature amount and the gradient information is input in parallel, a configuration that can calculate and store the gradient histogram with a smaller-scale circuit is required as compared with the configuration of the learning module 20 described above with reference to FIG. 17 to FIG. 20 . The following describes a configuration and an operation of the learning module according to the present embodiment with reference to FIG. 21 to FIG. 26 .

Configuration of Learning Module According to Second Embodiment

FIG. 21 is a diagram illustrating an example of a module configuration of the learning module of the learning and discrimination device according to the second embodiment. With reference to FIG. 21 , the following describes a configuration and an operation of a learning module 20 a of the learning and discrimination device (an example of a learning device) according to the present embodiment. In FIG. 21 , the number of division for Data Parallel is assumed to be 2, and the feature amount is assumed to have one dimension.

As illustrated in FIG. 21 , the learning module 20 a according to the present embodiment includes a gradient histogram calculating module 71, an accumulated gradient calculating module 72, a calculating module 73, and the optimum condition deriving module 22.

The gradient histogram calculating module 71 is a module that calculates, using each value of the feature amount of the input sample data as a bin of the histogram, the gradient histogram by integrating values of the gradient information corresponding to the sample data. The gradient histogram calculating module 71 includes gradient output modules 301 a and 301 b, an addition module 302, an accumulator module 303, and a sum total storing memory 304.

Each of the gradient output modules 301 a and 301 b is a module that includes an output port corresponding to each value of the feature amount, receives an input of the feature amount and the gradient information from the data memories 30 a and 30 b, and outputs the gradient information through the output port corresponding to a value of the input feature amount.

The addition module 302 is a module that adds up corresponding pieces of gradient information to be output for each value (bin) of the feature amount.

The accumulator module 303 is a module that adds the added gradient information input from the addition module 302 to the added gradient information that is presently held for each value (bin) of the feature amount, and holds the gradient histogram of the gradient information for each bin in the end.

The sum total storing memory 304 is a memory that stores the sum total of the gradient information calculated by the addition module 302.

The accumulated gradient calculating module 72 is a module that calculates the sums (G_(L), G_(R), H_(L), H_(R)) of the gradient information by obtaining the cumulative sum of the gradient histogram for each threshold of the feature amount.

The calculating module 73 is a module that calculates the branch score at each threshold using the expression (19) described above and using the sum of the gradient information calculated by the accumulated gradient calculating module 72.

The optimum condition deriving module 22 is a module that receives an input of the branch score corresponding to each feature amount (in FIG. 21 , one feature amount) and each threshold output from the calculating module 73, and derives a threshold and a number of the feature amount (feature amount number) the branch score of which is the largest. The optimum condition deriving module 22 writes the derived feature amount number and threshold into the model memory 40 as branch condition data of a corresponding node (an example of data of the node).

As illustrated in FIG. 21 , to implement Data Parallel in a case in which the number of division is 2, the memory is divided into two memories, that is, the data memories 30 a and 30 b, and the gradient histogram calculating module 71 is divided into two modules, that is, the gradient output modules 301 a and 301 b at a preceding stage. In FIG. 21 , a physical division unit is represented as “division 1” and “division 2”.

Configuration and Operation of Gradient Histogram Calculating Module

FIG. 22 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module of the learning module according to the second embodiment. With reference to FIG. 22 , the following describes a configuration and an operation of the gradient histogram calculating module 71 in the learning module 20 a according to the present embodiment. FIG. 21 illustrates a case in which the number of division for Data Parallel is assumed to be 2, the feature amount is assumed to have one dimension, and the gradient information is assumed to include only one piece of information (for example, the first-order gradient g).

As illustrated in FIG. 22 , the gradient histogram calculating module 71 includes data counters 311 a and 311 b in addition to the configuration described above with reference to FIG. 22 .

The data counter 311 a outputs an address for reading out the sample data (feature amount) to be subjected to learning processing and corresponding gradient information from the data memory 30 a.

As illustrated in FIG. 22 , the gradient output module 301 a includes comparators 312_1, 312_2, . . . , and 312_N and multiplexers 313_1, 313_2, . . . , and 313_N. In this case, N is a number of a value that may be taken by the feature amount, and is the number of bins in the gradient histogram. In a case of indicating an optional comparator among the comparators 312_1, 312_2, . . . , and 312_N, or a case in which the comparators 312_1, 312_2, . . . , and 312_N are collectively called, they are simply referred to as a “comparator 312”. In a case of indicating an optional multiplexer among the multiplexers 313_1, 313_2, . . . , and 313_N, or a case in which the multiplexers 313_1, 313_2, . . . , and 313_N are collectively called, they are simply referred to as a “multiplexer 313”.

The comparator 312 receives an input of values of the feature amount read out from the data memory 30 a and the feature amount of a specific bin, and compares the values with each other. If the values are identical to each other, the comparator 312 outputs the fact that the values are identical to each other (for example, an ON output of a voltage level) to the multiplexer 313. For example, in a case in which the feature amount read out from the data memory 30 a is identical to the value of the feature amount of a bin 1, the comparator 312_1 outputs the fact that the values are identical to each other to the multiplexer 313_1.

The multiplexer 313 receives an input of 0 and the gradient information corresponding to the feature amount (learning data) that is read out from the data memory 30 a by the comparator 312, and outputs the input gradient information or 0 in accordance with a comparison result output from the comparator 312. For example, the multiplexer 313_1 receives an input of 0 and the gradient information corresponding to the feature amount that is read out from the data memory 30 a by the comparator 312_1, outputs the input gradient information as the gradient information corresponding to the bin 1 in a case in which the comparison result output from the comparator 312_1 indicates that the values are identical to each other, and outputs 0 in a case in which the comparison result indicates that the values are not identical to each other. That is, in this mechanism, the gradient information corresponding to the feature amount is output from the multiplexer 313 corresponding to the value of the feature amount read out from the data memory 30 a, and 0 is output from the other multiplexer 313.

Functions of the data memory 30 b, the data counter 311 b, and the gradient output module 301 b are the same as those of the data memory 30 a, the data counter 311 a, and the gradient output module 301 a described above, respectively.

The addition module 302 adds up the gradient information input from the multiplexer 313 for each value of the feature amount, that is, for each bin, and outputs the added gradient information to the accumulator module 303. The addition module 302 includes adders 321_1, 321_2, . . . , and 321_N, and an adder 322.

Each of the adders 321_1, 321_2, . . . , and 321_N adds up the gradient information input from the multiplexer 313 for each of bins 1, 2, . . . , and N, and outputs the added gradient information to the accumulator module 303. For example, the adder 321_1 adds the gradient information as an output from the multiplexer 313_1 corresponding to the bin 1 in the gradient output module 301 a to the gradient information as an output from the multiplexer 313_1 corresponding to the bin 1 in the gradient output module 301 b, and outputs the added gradient information to the accumulator module 303 (in this case, a bin 1 accumulator 331_1 described later).

The adder 322 receives an input of the pieces of gradient information to be added up, the pieces of gradient information read out from the data memories 30 a and 30 b by the gradient output module 301 a and the gradient output module 301 b, respectively. The adder 322 then outputs the added gradient information to the sum total storing memory 304.

The accumulator module 303 adds the added gradient information input from the addition module 302 to the added gradient information that is presently held for each value (bin) of the feature amount, and holds the gradient histogram of the gradient information for each bin in the end. The accumulator module 303 includes the bin 1 accumulator 331_1, a bin 2 accumulator 331_2, . . . , and a bin N accumulator 331_N.

The bin 1 accumulator 331_1, the bin 2 accumulator 331_2, . . . , and the bin N accumulator 331_N adds the added gradient information input from the respective adders 321_1, 321_2, . . . , and 321_N to the added gradient information that is presently held for each of the bins 1, 2, . . . , and N. For example, the bin 1 accumulator 331_1 adds the added gradient information input from the adder 321_1 to the added gradient information that is presently held, and holds the gradient histogram of the gradient information of the bin 1.

The sum total storing memory 304 adds the added gradient information output from the adder 322 to the added gradient information that is presently held. That is, the sum total storing memory 304 stores the sum total of the gradient information corresponding to all the pieces of learning data.

The following simply describes an operation procedure of calculating the gradient histogram performed by the gradient histogram calculating module 71 according to the present embodiment. The data counter 311 a (311 b) outputs an address for reading out the sample data (feature amount) to be subjected to learning processing and corresponding gradient information from the data memory 30 a. The comparator 312 of the gradient output module 301 a (301 b) receives an input of values of the feature amount read out from the data memory 30 a (30 b) and the feature amount of a specific bin, and compares the values with each other. If the values are identical to each other, the comparator 312 outputs the fact that the values are identical to each other to the multiplexer 313. The multiplexer 313 receives an input of 0 and the gradient information corresponding to the feature amount (learning data) that is read out from the data memory 30 a (30 b) by the comparator 312, and outputs 0 or the input gradient information in accordance with a comparison result output from the comparator 312. The respective adders 321_1, 321_2, . . . , and 321_N of the addition module 302 add up the gradient information input from the multiplexer 313 for each of the bins 1, 2, . . . , and N, and output the added gradient information to the accumulator module 303. The bin 1 accumulator 331_1, the bin 2 accumulator 331_2, . . . , and the bin N accumulator 331_N of the accumulator module 303 add the added gradient information input from the respective adders 321_1, 321_2, . . . , and 321_N to the added gradient information that is presently held for each of the bins 1, 2, . . . , and N, and holds the gradient histogram of the gradient information for each bin in the end. The above operation is repeatedly performed on all the pieces of learning data at the present node.

In the configuration of the gradient histogram calculating module 71 according to the present embodiment as described above, the gradient histogram is stored in a corresponding register (accumulator) for each bin of the feature amount instead of being stored in the memory as in the conventional configuration illustrated in FIG. 20 . The configuration of the gradient histogram calculating module 71 illustrated in FIG. 22 can be implemented with registers the number of which is equal to (the number of bins of the feature amount×the dimensions of the feature amount (in FIG. 22 , the number of dimensions is assumed to be one)). That is, the total capacity required for storing the gradient histogram is represented as (the number of bins×the bit width×2 (the first-order gradient g, the second-order gradient h)×the dimensions of the feature amount), which does not depend on the number of division. Thus, as compared with the conventional configuration illustrated in FIG. 20 , circuit capacity for storing the gradient histogram can be greatly reduced. Additionally, in the configuration of the gradient histogram calculating module 71 according to the present embodiment, a circuit scale does not depend on the number of division, so that the number of division for Data Parallel can be increased so long as a circuit scale of other modules allows, and speed of learning processing can be improved.

For example, in a case in which the feature amount is 8 bits (256 patterns) and has 2000 dimensions, and the gradient information includes two gradients, that is, the first-order gradient g and the second-order gradient h, the number of required registers is represented as follows. 256 (the number of bins)×2 (the first-order gradient g, the second-order gradient h)×2000 [dimensions]=1024000 [registers]

In a case of a chip called VU9P described above, the maximum number of registers is 2364000, so that the number of registers required for holding the gradient histogram can be suppressed to be substantially half of the maximum number of registers in the configuration of the gradient histogram calculating module 71 according to the present embodiment.

FIG. 23 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module in a case in which the number of division is assumed to be 3 in the learning module according to the second embodiment. With reference to FIG. 23 , the following describes a configuration example of the gradient histogram calculating module 71 in a case in which the number of division for Data Parallel is assumed to be 3. FIG. 23 illustrates a case in which the feature amount is assumed to have one dimension, and the gradient information is assumed to include only one piece of information (for example, the first-order gradient g).

For example, in FIG. 23 , the addition module 302 includes adders 321_1_1, . . . , and 321_N_1, adders 321_1_2, . . . , and 321_N_2, and adders 322_1 and 322_2. As in the gradient histogram calculating module 71 illustrated in FIG. 23 , the addition module 302 may integrate (add up) the pieces of gradient information in a stepwise manner. For example, regarding the bin 1, the adder 321_1_1 adds the gradient information output from “division 1” to the gradient information output from “division 2” to be output to the adder 321_1_2. The adder 321_1_2 adds an added value output from the adder 321_1_1 to the gradient information output from “division 3” to be output to the bin 1 accumulator 331_1 of the accumulator module 303.

Configuration and Operation of Accumulated Gradient Calculating Module

FIG. 24 is a diagram illustrating an example of a module configuration of the accumulated gradient calculating module of the learning module according to the second embodiment. With reference to FIG. 24 , the following describes a configuration and an operation of the accumulated gradient calculating module 72 in the learning module 20 a according to the present embodiment. FIG. 24 illustrates a case in which the number of division for Data Parallel is assumed to be 1, the feature amount is assumed to have one dimension, and the gradient information is assumed to include two piece of information (for example, the first-order gradient g and the second-order gradient h).

The conventional accumulated gradient calculating module 62 illustrated in FIG. 19 accesses the gradient histogram memory 204 (208) using the output (threshold) from the threshold counter 210 as an address. In FIG. 24 , the gradient histogram is held by the register (accumulator) for each bin, so that only a value corresponding to the threshold of the threshold counter is extracted from every bin via the multiplexer.

As illustrated in FIG. 24 , the accumulated gradient calculating module 72 includes a threshold counter 340, an accumulator 341, a delay 342, a difference calculator 343, an accumulator 344, a delay 345, a difference calculator 346, and multiplexers 347 and 348. In FIG. 24 , the accumulator module 303 and the sum total storing memory 304 corresponding to the first-order gradient g are assumed to be an accumulator module 303 g and a sum total storing memory 304 g, respectively. The accumulator module 303 and the sum total storing memory 304 corresponding to the second-order gradient h are assumed to be an accumulator module 303 h and a sum total storing memory 304 h, respectively.

The threshold counter 340 outputs a threshold for reading out, from the accumulator modules 303 g and 303 h, the gradient information (g, h) added for each value (bin) of the feature amount, that is, the gradient histogram of each bin of the feature amount.

The multiplexer 347 receives an input of the threshold from the threshold counter 340, and an input of a storage value (gradient histogram) of each accumulator (the bin 1 accumulator 331_1, the bin 2 accumulator 331_2, . . . , and the bin N accumulator 331_N) of the accumulator module 303 g. The multiplexer 347 then outputs, to the accumulator 341, the gradient histogram corresponding to the bin corresponding to the threshold from the threshold counter 340 among the input gradient histograms of the respective bins.

The multiplexer 348 receives an input of the threshold from the threshold counter 340, and an input of the storage value (gradient histogram) of each accumulator (the bin 1 accumulator 331_1, the bin 2 accumulator 331_2, . . . , and the bin N accumulator 331_N) of the accumulator module 303 h. The multiplexer 348 then outputs, to the accumulator 344, the gradient histogram corresponding to the bin corresponding to the threshold from the threshold counter 340 among the input gradient histograms of the respective bins.

The accumulator 341 receives, from the multiplexer 347, an input of the gradient histogram of the gradient information g corresponding to the threshold output from the threshold counter 340, accumulates the input gradient histogram on the cumulative sum of the gradient histogram that is presently stored, and holds it as a new cumulative sum of the gradient histogram.

The delay 342 outputs, as the sum G_(L) of the gradient information g, the cumulative sum of the gradient histogram of the gradient information g read out from the accumulator 341 with delay to be matched with a timing at which the sum G_(R) of the gradient information g is output from the difference calculator 343.

The difference calculator 343 calculates the sum G_(R) of the gradient information g by subtracting the cumulative sum of the gradient histogram of the gradient information g read out from the accumulator 341 (that is, the sum G_(L) of the gradient information g) from the sum total of the gradient information g read out from the sum total storing memory 304 g.

The accumulator 344 receives, from the multiplexer 348, an input of the gradient histogram of the gradient information h corresponding to the threshold output from the threshold counter 340, accumulates the input gradient histogram on the cumulative sum of the gradient histogram that is presently stored, and holds it as a new cumulative sum of the gradient histogram.

The delay 345 outputs, as the sum H_(L) of the gradient information h, the cumulative sum of the gradient histogram of the gradient information h read out from the accumulator 344 with delay to be matched with a timing at which the sum H_(R) of the gradient information h is output from the difference calculator 346.

The difference calculator 346 calculates the sum H_(R) of the gradient information h by subtracting the cumulative sum of the gradient histogram of the gradient information h read out from the accumulator 344 (that is, the sum H_(L) of the gradient information h) from the sum total of the gradient information h read out from the sum total storing memory 304 h.

The following simply describes an operation procedure of calculating the sums (G_(L), G_(R), H_(L), H_(R)) of the gradient information performed by the accumulated gradient calculating module 72. The accumulated gradient calculating module 72 starts calculation processing after the gradient histogram calculating module 71 ends the operation of calculation and storage processing for the gradient histogram of the gradient information. That is, after the gradient histogram calculating module 71 ends the calculation processing, the accumulator modules 303 g and 303 h hold the gradient histograms of the respective pieces of gradient information g and h calculated from all the pieces of learning data of the present node.

First, the multiplexer 347 receives an input of the threshold from the threshold counter 340, and an input of the storage value (gradient histogram) of each accumulator (the bin 1 accumulator 331_1, the bin 2 accumulator 331_2, . . . , and the bin N accumulator 331_N) of the accumulator module 303 g. The multiplexer 347 outputs, to the accumulator 341, the gradient histogram corresponding to the bin corresponding to the threshold from the threshold counter 340 among the input gradient histograms of the respective bins. The accumulator 341 then receives, from the multiplexer 347, an input of the gradient histogram of the gradient information g corresponding to the threshold output from the threshold counter 340, accumulates the input gradient histogram on the cumulative sum of the gradient histogram that is presently stored, and holds it as a new cumulative sum of the gradient histogram. The delay 342 outputs, to the calculating module 73, the cumulative sum of the gradient histogram of the gradient information g read out from the accumulator 341 with delay to be matched with a timing at which the sum G_(R) of the gradient information g is output from the difference calculator 343, as the sum G_(L) of the gradient information g. The difference calculator 343 calculates the sum G_(R) of the gradient information g by subtracting the cumulative sum of the gradient histogram of the gradient information g read out from the accumulator 341 (that is, the sum G_(L) of the gradient information g) from the sum total of the gradient information g read out from the sum total storing memory 304 g, and outputs the sum G_(R) to the calculating module 73. The same applies to processing on the gradient information h (calculation processing for the sum H_(L) and H_(R) of the gradient information h) performed by the multiplexer 348, the accumulator 344, the delay 345, and the difference calculator 346. The above operation is repeatedly performed on all of the thresholds, and this is implemented when the threshold counter 340 sequentially counts up the thresholds to be output in a round.

In this way, the accumulated gradient calculating module 72 and the calculating module 73 performs the processing after the gradient histogram calculating module 71 performs the operation of calculation and storage processing for the gradient histogram of the gradient information in advance. Due to this, speed of calculation processing for the branch score (gain) performed by the learning module 20 a can be increased.

Configuration of Learning Module in a Case in which Number of Dimensions is 2

FIG. 25 is a diagram illustrating an example of a module configuration of the learning module in a case in which the number of types of feature amounts is assumed to be 2 in the learning and discrimination device according to the second embodiment. FIG. 26 is a diagram illustrating an example of a module configuration of the gradient histogram calculating module in a case in which the number of types of feature amounts is assumed to be 2 in the learning module according to the second embodiment. With reference to FIG. 25 and FIG. 26 , the following describes a configuration and an operation of a learning module 20 b of the learning and discrimination device (an example of a learning device) according to the present embodiment. FIG. 25 illustrates a case in which the number of division for Data Parallel is assumed to be 2, and the feature amount is assumed to have two dimensions.

As illustrated in FIG. 25 , the learning module 20 b includes the gradient histogram calculating module 71, accumulated gradient calculating modules 72_1 and 72_2, calculating modules 73_1 and 73_2, and the optimum condition deriving module 22. The gradient histogram calculating module 71 includes gradient output modules 301 a_1, 301 a_2, 301 b_1, and 301 b_2, addition modules 302_1 and 302_2, accumulator modules 303_1 and 303_2, and sum total storing memories 304_1 and 304_2. As illustrated in FIG. 26 , the gradient histogram calculating module 71 includes the data counters 311 a and 311 b in addition to the configuration illustrated in FIG. 25 .

As illustrated in FIG. 26 , each of the gradient output modules 301 a_1, 301 a_2, 301 b_1, and 301 b_2 includes the comparators 312_1, 312_2, . . . , and 312_N, and the multiplexers 313_1, 313_2, . . . , and 313_N. Each of the addition modules 302_1 and 302_2 includes the adders 321_1, 321_2, . . . , and 321_N, and the adder 322. Each of the accumulator modules 303_1 and 303_2 includes the bin 1 accumulator 331_1, the bin 2 accumulator 331_2, . . . , and the bin N accumulator 331_N.

In the configuration illustrated in FIG. 25 and FIG. 26 , the gradient output modules 301 a_1 and 301 b_1, the addition module 302_1, the accumulator module 303_1, the sum total storing memory 304_1, the accumulated gradient calculating module 72_1, and the calculating module 73_1 are used for processing corresponding to “feature amount 1”. On the other hand, the gradient output modules 301 a_2 and 301 b_2, the addition module 302_2, the accumulator module 303_2, the sum total storing memory 304_2, the accumulated gradient calculating module 72_2, and the calculating module 73_2 are used for processing corresponding to “feature amount 2”. An operation of each of the modules is the same as the operation described above with reference to FIG. 22 and FIG. 24 .

As described above, the capacity required for storing the gradient histogram is represented as (the number of bins×the bit width×2 (the first-order gradient g, the second-order gradient h)×the dimensions of the feature amount), so that the accumulator modules 303 the number of which corresponds to the dimensions of the feature amount are required (in FIG. 25 , the accumulator modules 303_1 and 303_2). However, the capacity does not depend on the number of division, so that, although FIG. 25 and FIG. 26 exemplify the case in which the number of division is 2, it is sufficient to arrange the two accumulator modules 303 so long as the dimensions of the feature amount is two even when the number of division becomes equal to or larger than 3.

As described above, in the learning module 20 a (20 b) of the learning and discrimination device according to the present embodiment, the gradient histogram calculating module 71 stores the gradient histogram in a corresponding register (accumulator) for each bin of the feature amount instead of storing the gradient histogram in the memory as in the conventional configuration illustrated in FIG. 20 . The configuration of the gradient histogram calculating module 71 can be implemented with registers the number of which is equal to (the number of bins of the feature amount×the dimensions of the feature amount). That is, the total capacity required for storing the gradient histogram is represented as (the number of bins×the bit width×2 (the first-order gradient g, the second-order gradient h)×the dimensions of the feature amount), which does not depend on the number of division. Thus, as compared with the conventional configuration illustrated in FIG. 20 , it is possible to greatly reduce the circuit scale of the memory (the accumulator, the register) that holds the information of the gradient histogram created for the feature amount and the gradient information that are input in parallel. Additionally, in the configuration of the gradient histogram calculating module 71 according to the present embodiment, the circuit scale does not depend on the number of division, so that the number of division for Data Parallel can be increased so long as the circuit scale of the other modules allows, and speed of learning processing can be improved.

Third Embodiment

The following describes the learning and discrimination device according to a third embodiment, mainly about differences from the learning and discrimination device according to the second embodiment. The present embodiment describes a hard logic configuration of a control module that implements address calculation for the learning data in a case of dividing the learning data at the node into pieces to perform learning in parallel in the learning processing by the GBDT (that is, in a case of performing learning by Data Parallel).

Configuration of Learning and Discrimination Device

FIG. 27 is a diagram illustrating an example of a module configuration of the learning and discrimination device according to the third embodiment. FIG. 28 is a diagram for explaining address calculation for the learning data at a node as the next learning target. With reference to FIG. 27 and FIG. 28 , the following describe a module configuration of a learning and discrimination device 1 b (an example of a learning device) according to the present embodiment. The learning and discrimination device according to the present embodiment performs address calculation for the learning data by Data Parallel, but in the following description, the learning and discrimination device 1 b illustrated in FIG. 27 is assumed to have a configuration not using Data Parallel for firstly explaining an operation of calculating the address performed by an address manager 12 described below.

As illustrated in FIG. 28 , the learning and discrimination device 1 b according to the present embodiment includes a control module 15, the learning module 20, the data memory 30, the model memory 40, and the classification module 50. Among these, the learning module 20, the data memory 30, the model memory 40, and the classification module 50 are configured by an FPGA, for example. The control module 15 can perform data communication with the FPGA via a bus. In addition to the components illustrated in FIG. 27 , the learning and discrimination device 1 b may include other components such as an auxiliary storage device storing various kinds of data (a computer program and the like) and a communication I/F for communicating with an external device, for example. The configuration and the operation of the learning module 20, the data memory 30, the model memory 40, and the classification module 50 are the same as those described in the first embodiment and the second embodiment.

The control module 15 is an arithmetic module that controls learning by the GBDT as a whole. The control module 15 includes the CPU 10 and the address manager 12 (manager). The CPU 10 includes the control unit 11.

The control unit 11 controls respective modules including the learning module 20, the data memory 30, the model memory 40, and the classification module 50. The control unit 11 is implemented by a computer program executed by the CPU 10.

The address manager 12 is a hard logic module that receives a node address (as described later, a number for discriminating a node at each depth) and a selection signal for designating a bank A or a bank B from the control unit 11, receives an intermediate address from the classification module 50 that has ended discrimination processing, and calculates a start address and an end address for performing learning of the next node. The following describes a specific operation of calculating the address performed by the address manager 12 with reference to FIG. 28 .

Learning processing by the GBDT is performed in units of a node as described above. When learning of the node is ended, to determine the learning data to be used for learning of the next node, the learning data is made to branch by the classification module 50 to update the pointer memory, and the intermediate address described above is calculated. To recognize a range of addresses of the learning data stored in the pointer memory 31 to be used for learning in learning of the next node, it is required to calculate the range from the start address, the end address (first address), and the intermediate address (second address) of the present node (first node) to be stored, which is performed by the address manager 12 as a module.

A target of the GBDT herein is a binary tree, so that the address manager 12 calculates addresses on the pointer memory 31 corresponding to respective pieces of learning data branched to nodes branching to the left and the right after learning of one node. That is, the address manager 12 calculates two start addresses (third addresses) and two end addresses (third addresses) corresponding to the next two nodes (second nodes) from the start address, the end address, and the intermediate address of the present node. FIG. 28 illustrates an operation of calculating the address performed by the address manager 12. In FIG. 28 , start_address, end_address, and mid_address respectively indicate the start_address, the end_address, and the intermediate address of the present node. From these three addresses, start_address_1 and start_address_2 as the start addresses of the next two nodes, and end_address_1 and end_address_2 as the two end addresses are calculated by the following expression (23). start_address_1=start_address end_address_1=mid_address start_address_2=mid_address+1 end_address_2=end_address  (23)

The address calculation processing itself performed by the address manager 12 is simple as described above, and the addresses can be calculated by a soft processor such as PicoBlaze and MicroBlaze. However, in a case of performing learning by Data Parallel, the address needs to be calculated for each division. For example, in a case of dividing the learning data into 100 pieces, 100 times of address calculation processing is required for each node. In a case of calculating the address by a soft processor, several clocks to several tens of clocks are required, so that the number of clocks required for address calculation becomes a bottleneck in a case of performing learning by Data Parallel. In a case of including one address manager although using hard logic, when the learning data is divided into 100 pieces, 100 times of address calculation needs to be directly performed. Thus, in the present embodiment, a function of calculating the address is implemented by hard logic, and the address manager 12 configured by hard logic for each division is provided to increase the speed of address calculation processing as described later. A specific configuration of hard logic of the address manager 12 will be described later with reference to FIG. 29 to FIG. 32 .

Configuration of Address Manager

FIG. 29 is a diagram illustrating an example of a module configuration of the address manager according to the third embodiment. FIG. 30 is a diagram illustrating an example of a module configuration of an address calculator 121 according to the third embodiment. FIG. 31 is a diagram for explaining a node address. FIG. 32 is a diagram illustrating an example of a configuration of the address memory according to the third embodiment. The following describes a configuration of the address manager 12 with reference to FIG. 29 to FIG. 32 .

The address manager 12 includes the address calculator 121, an address storage destination control unit 122, an address memory 123, and an output selector 124.

The address calculator 121 calculates two start addresses and two end addresses corresponding to the next two nodes using the expression 23 described above based on the node address (referred to as a node address n) of the present node (referred to as a node n) received from the control unit 11, the intermediate address received from the classification module 50 that is determined after learning of the present node, and the start address and the end address of the node n. Specifically, the address calculator 121 calculates the start address and the end address of a node 2n, and the start address and the end address of a node 2(n+1). The address calculator 121 then transmits, to the address storage destination control unit 122, the calculated addresses and storage addresses (node addresses 2n, 2(n+1)) indicating storage destinations of the addresses.

Specifically, as illustrated in FIG. 30 , the address calculator 121 includes a multiplier 131, an adder 132, and an adder 133.

The multiplier 131 is an arithmetic circuit that outputs the node address 2n obtained by multiplying the input node address n by 2. The adder 132 is an arithmetic circuit that adds 1 to the node address 2n calculated by the multiplier 131 to output the node address 2n+1. The adder 133 is an arithmetic circuit that outputs an address obtained by adding 1 to the input intermediate address as the start address of the node 2(n+1).

The address calculator 121 outputs the input start address of the node n as the start address of the node 2n. The address calculator 121 also outputs the input intermediate address as the end address of the node 2n. The address calculator 121 outputs the input end address of the node n as the end address of the node 2(n+1). An arithmetic operation based on the expression (23) described above is implemented by the configuration and the operation of the address calculator 121 described above.

The address storage destination control unit 122 is a module that stores each address calculated by the address calculator 121 in a storage region indicated by a storage address in each memory of the address memory 123 (a start address memory 123A_ST for the bank A and an end address memory 123A_ED for the bank A, or a start address memory 123B_ST for the bank B and an end address memory 123B_ED for the bank B) corresponding to the bank (the bank A or the bank B) designated by the selection signal received from the control unit 11. For example, in a case in which the selection signal indicates the bank A, and the storage address indicates the node address 0, 1, the address storage destination control unit 122 stores the start address and the end address of a node 0 as the next node in each storage region indicated by the node address 0 in the start address memory 123A_ST for the bank A and the end address memory 123A_ED for the bank A. The address storage destination control unit 122 also stores the start address and the end address of a node 1 as the next node in each storage region indicated by the node address 1 in the start address memory 123A_ST for the bank A and the end address memory 123A_ED for the bank A.

The address memory 123 is a memory that stores two start addresses and two end addresses corresponding to the next two nodes calculated by the address calculator 121. The address memory 123 includes the start address memory 123A_ST for the bank A, the start address memory 123B_ST for the bank B, the end address memory 123A_ED for the bank A, and the end address memory 123B_ED for the bank B.

The start address memory 123A_ST for the bank A stores the start address corresponding to the next node as an address for referring to the bank A. The start address memory 123B_ST for the bank B stores the start address corresponding to the next node as an address for referring to the bank B. The end address memory 123A_ED for the bank A stores the end address corresponding to the next node as an address for referring to the bank A. The end address memory 123B_ED for the bank B stores the end address corresponding to the next node as an address for referring to the bank B.

For example, FIG. 32 illustrates the configuration of the start address memory 123A_ST for the bank A. The start address memory 123A_ST for the bank A includes storage regions each of which is specified by an address that is called the node address. In the example illustrated in FIG. 32 , the storage regions constituting the start address memory 123A_ST for the bank A are respectively specified by the node addresses 0, 1, . . . , and N. The start address memory 123B_ST for the bank B, the end address memory 123A_ED for the bank A, and the end address memory 123B_ED for the bank B each have the same configuration as that illustrated in FIG. 32 .

The following describes the node address with reference to FIG. 31 . In the decision tree illustrated in FIG. 31 , as described above in the first embodiment, it is assumed that the top of a hierarchy is referred to as “depth 0”, hierarchical levels lower than the top are referred to as “depth 1”, “depth 2”, . . . in order, the leftmost node at a specific hierarchical level is referred to as “node 0”, and nodes on the right side thereof are referred to as “node 1”, “node 2”, . . . in order. In this case, an address for indicating a node at a specific hierarchical level in the decision tree is the node address. For example, the node address 1 is an address indicating the second node from the left at a specific hierarchical level, that is, the node 1. Assuming that the node address of the present node is n, the node addresses of the next nodes are 2n and 2n+1, which are calculated by the address calculator 121 as described above.

The output selector 124 is a module that reads out the start address and the end address corresponding to the next node from the storage region of the memory specified based on the node address and the selection signal received from the control unit 11 among the four memory included in the address memory 123, and outputs the start address and the end address to the learning module 20. For example, in a case in which the selection signal received from the control unit 11 indicates the bank B, and the node address 2 is received from the control unit 11, the output selector 124 reads out the start address from the storage region specified by the node address 2 in the start address memory 123B_ST for the bank B, reads out the end address from the storage region specified by the node address 2 in the end address memory 123B_ED for the bank B, and outputs the start address and the end address.

Address Management Performed by Address Manager

The following specifically describes address management performed by the address manager 12 with reference to FIG. 33 to FIG. 37 .

Before Learning at Depth 0, Node 0

FIG. 33 is a diagram illustrating a state of the address memory before learning at depth 0, node 0 performed by the learning and discrimination device according to the third embodiment.

As illustrated in FIG. 33 , before learning at depth 0, node 0, that is, in an initial state, for example, the start address (0) in the bank A corresponding to depth 0, node 0 (a node at the top of the decision tree) is stored at the node address 0 in the start address memory 123A_ST for the bank A. The end address (max address) in the bank A corresponding to depth 0, node 0 is stored at the node address 0 in the end address memory 123A_ED for the bank A. In this case, max address is a value substantially representing a total number of pieces of the learning data. In the initial state in FIG. 33 , both of the start address and the end address are not written into the start address memory 123B_ST for the bank B and the end address memory 123B_ED for the bank B.

In FIG. 33 to FIG. 37 , it is assumed that an indefinite value is written into the storage region in which “X” is written. As a separate initialization step of causing the initial state, a certain initial value may be stored therein. In FIG. 33 to FIG. 37 , the storage region hatched by oblique lines indicates a storage region into which data is written, and the storage region hatched by dots indicates a storage region from which data is read out.

After Learning at Depth 0, Node 0

FIG. 34 is a diagram illustrating a state of the address memory after learning at depth 0, node 0 performed by the learning and discrimination device according to the third embodiment.

At the time of learning at depth 0, node 0, the bank A serves as a read-out bank, and the bank B serves as a writing bank. The output selector 124 reads out the start address (0) and the end address (max address) from the storage region specified by the node address 0 and the selection signal indicating the bank A received from the control unit 11, that is, the node address 0 in each of the start address memory 123A_ST for the bank A and the end address memory 123A_ED for the bank A, and outputs the start address (0) and the end address (max address) to the learning module 20.

The learning module 20 reads out the address of target learning data from the bank A based on the start address and the end address, and reads out learning data (feature amount) from the feature memory 32 based on the address to perform learning. The learning module 20 writes the feature amount number and the threshold derived through learning into the model memory 40 as branch condition data at depth 0, node 0.

The classification module 50 receives the same start address and end address from the address manager 12, reads out the address of the target learning data from the bank A based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 reads out the branch condition data (the feature amount number, the threshold) at depth 0, node 0 from the model memory 40. The classification module 50 determines whether to cause the read-out sample data to branch to the left side or to the right side of depth 0, node 0 in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the bank B serving as a writing bank for the pointer memory 31. At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address (from the start address (0)) in the bank B. If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address (from the end address (max address)) in the bank B. The classification module 50 then returns, to the address manager 12, an address (intermediate address) in the bank B corresponding to a boundary between the address of the learning data branched to the left side and the address of the learning data branched to the right side. The intermediate address is used for the next branch processing.

The address calculator 121 calculates two start addresses and two end addresses corresponding to the next two nodes using the expression (23) described above based on the node address 0 of the present node (depth 0, node 0) received from the control unit 11, the intermediate address received from the classification module 50, and the start address and the end address of the present node. Specifically, the address calculator 121 calculates the start address and the end address at depth 1, node 0, and the start address and the end address at depth 1, node 1. The address calculator 121 then transmits, to the address storage destination control unit 122, the calculated addresses and storage addresses (node addresses 0, 1) indicating storage destinations of the addresses.

The address storage destination control unit 122 stores the respective addresses calculated by the address calculator 121 in storage regions indicated by the storage addresses (node addresses 0, 1) in the start address memory 123B_ST for the bank B and the end address memory 123B_ED for the bank B corresponding to the bank B designated by the selection signal received from the control unit 11. Specifically, the address storage destination control unit 122 stores the start address (0) in the bank B corresponding to depth 1, node 0 at the node address 0 in the start address memory 123B_ST for the bank B, and stores the end address (mid_address_0_0) in the bank B corresponding to depth 1, node 0 at the node address 0 in the end address memory 123B_ED for the bank B. In this case, “mid_address_a_b” indicates an intermediate address at depth a, node b. Furthermore, the address storage destination control unit 122 stores the start address (mid_address_0_0+1) in the bank B corresponding to depth 1, node 1 at the node address 1 in the start address memory 123B_ST for the bank B, and stores the end address (max address) in the bank B corresponding to depth 1, node 1 at the node address 1 in the end address memory 123B_ED for the bank B.

After Learning at Depth 1, Node 0

FIG. 35 is a diagram illustrating a state of the address memory after learning at depth 1, node 0 by the learning and discrimination device according to the third embodiment.

At the time of learning at depth 1, node 0, the bank B serves as a read-out bank, and the bank A serves as a writing bank. The output selector 124 reads out the start address (0) and the end address (mid_address_0_0) from the storage region specified by the node address 0 and the selection signal indicating the bank B received from the control unit 11, that is, the node address 0 of each of the start address memory 123B_ST for the bank B and the end address memory 123B_ED for the bank B, and outputs the start address (0) and the end address (mid_address_0_0) to the learning module 20.

The learning module 20 reads out the address of the target learning data from the bank B based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address to perform learning. The learning module 20 writes the feature amount number and the threshold derived through learning into the model memory 40 as the branch condition data at depth 1, node 0.

The classification module 50 receives the same start address and end address from the address manager 12, reads out the address of the target learning data from the bank B based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 also reads out the branch condition data (the feature amount number, the threshold) at depth 1, node 0 from the model memory 40. The classification module 50 determines whether to cause the read-out sample data to branch to the left side or to the right side of depth 1, node 0 in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the bank A serving as a writing bank for the pointer memory 31. At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address (from the start address (0)) in the bank A. If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address (from the end address (mid_address_0_0)) in the bank A. The classification module 50 then returns, to the address manager 12, an address (intermediate address) in the bank A corresponding to a boundary between the address of the learning data branched to the left side and the address of the learning data branched to the right side. The intermediate address is used for the next branch processing.

The address calculator 121 calculates two start addresses and two end addresses corresponding to the next two nodes using the expression (23) described above based on the node address 0 of the present node (depth 1, node 0) received from the control unit 11, the intermediate address received from the classification module 50, and the start address and the end address of the present node. Specifically, the address calculator 121 calculates the start address and the end address at depth 2, node 0, and the start address and the end address at depth 2, node 1. The address calculator 121 then transmits, to the address storage destination control unit 122, the calculated addresses and the storage addresses (node addresses 0, 1) indicating storage destinations of the addresses.

The address storage destination control unit 122 stores the respective addresses calculated by the address calculator 121 in storage regions indicated by the storage addresses (node addresses 0, 1) in the start address memory 123A_ST for the bank A and the end address memory 123A_ED for the bank A corresponding to the bank A designated by the selection signal received from the control unit 11. Specifically, the address storage destination control unit 122 stores the start address (0) in the bank A corresponding to depth 2, node 0 at the node address 0 in the start address memory 123A_ST for the bank A, and stores the end address (mid_address_1_0) in the bank A corresponding to depth 2, node 0 at the node address 0 in the end address memory 123A_ED for the bank A. Furthermore, the address storage destination control unit 122 stores the start address (mid_address_1_0+1) in the bank A corresponding to depth 2, node 1 at the node address 1 in the start address memory 123A_ST for the bank A, and stores the end address (mid_address_0_0) in the bank A corresponding to depth 2, node 1 at the node address 1 in the end address memory 123A_ED for the bank A.

After Learning at Depth 1, Node 1

FIG. 36 is a diagram illustrating a state of the address memory after learning at depth 1, node 1 performed by the learning and discrimination device according to the third embodiment.

At the time of learning at depth 1, node 1, the bank B serves as a read-out bank, and the bank A serves as a writing bank. The output selector 124 reads out the start address (mid_address_0_0+1) and the end address (max address) from the storage region specified by the node address 1 and the selection signal indicating the bank B received from the control unit 11, that is, the node address 1 of each of the start address memory 123B_ST for the bank B and the end address memory 123B_ED for the bank B, and outputs the start address (mid_address_0_0+1) and the end address (max address) to the learning module 20.

The learning module 20 reads out the address of the target learning data from the bank B based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address to perform learning. The learning module 20 writes the feature amount number and the threshold derived through learning into the model memory 40 as the branch condition data at depth 1, node 1.

The classification module 50 receives the same start address and end address from the address manager 12, reads out the address of the target learning data from the bank B based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 reads out the branch condition data (the feature amount number, the threshold) at depth 1, node 1 from the model memory 40. The classification module 50 then determines whether to cause the read-out sample data to branch to the left side or to the right side of depth 1, node 1 in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the bank A serving as a writing bank for the pointer memory 31. At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address (from the start address (mid_address0_0+1)) in the bank A. If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address (from the end address (max address)) in the bank A. The classification module 50 then returns, to the address manager 12, the address (intermediate address) in the bank A corresponding to a boundary between the address of the learning data branched to the left side and the address of the learning data branched to the right side. The intermediate address is used for the next branch processing.

The address calculator 121 calculates two start addresses and two end addresses corresponding to the next two nodes using the expression (23) described above based on the node address 1 of the present node (depth 1, node 1) received from the control unit 11, the intermediate address received from the classification module 50, and the start address and the end address of the present node. Specifically, the address calculator 121 calculates the start address and the end address at depth 2, node 2, and the start address and the end address at depth 2, node 3. The address calculator 121 then transmits, to the address storage destination control unit 122, the calculated addresses and the storage addresses (node addresses 2, 3) indicating storage destinations of the addresses.

The address storage destination control unit 122 stores the respective addresses calculated by the address calculator 121 in storage regions indicated by the storage addresses (node addresses 2, 3) in the start address memory 123A_ST for the bank A and the end address memory 123A_ED for the bank A corresponding to the bank A designated by the selection signal received from the control unit 11. Specifically, the address storage destination control unit 122 stores the start address (mid_address_0_0+1) in the bank A corresponding to depth 2, node 2 at the node address 2 in the start address memory 123A_ST for the bank A, and stores the end address (mid_address_1_1) in the bank A corresponding to depth 2, node 2 at the node address 2 in the end address memory 123A_ED for the bank A. Furthermore, the address storage destination control unit 122 stores the start address (mid_address_1_1+1) in the bank A corresponding to depth 2, node 3 at the node address 3 in the start address memory 123A_ST for the bank A, and stores the end address (max address) in the bank A corresponding to depth 2, node 3 at the node address 3 in the end address memory 123A_ED for the bank A.

After Learning at Depth 2, Node 0

FIG. 37 is a diagram illustrating a state of the address memory after learning at depth 2, node 0 performed by the learning and discrimination device according to the third embodiment.

At the time of learning at depth 2, node 0, the bank A serves as a read-out bank, and the bank B serves as a writing bank. The output selector 124 reads out the start address (0) and the end address (mid_adress_1_0) from the storage region specified by the node address 0 and the selection signal indicating the bank A received from the control unit 11, that is, the node address 0 in each of the start address memory 123A_ST for the bank A and the end address memory 123A_ED for the bank A, and outputs the start address (0) and the end address (mid_adress_1_0) to the learning module 20.

The learning module 20 reads out the address of the target learning data from the bank A based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address to perform learning. The learning module 20 writes the feature amount number and the threshold derived through learning into the model memory 40 as the branch condition data at depth 2, node 0.

The classification module 50 receives the same start address and end address from the address manager 12, reads out the address of the target learning data from the bank A based on the start address and the end address, and reads out the learning data (feature amount) from the feature memory 32 based on the address. The classification module 50 reads out the branch condition data (the feature amount number, the threshold) at depth 2, node 0 from the model memory 40. The classification module 50 determines whether to cause the read-out sample data to branch to the left side or to the right side of depth 2, node 0 in accordance with the branch condition data, and based on a determination result, the classification module 50 writes the address of the learning data in the feature memory 32 into the bank B serving as a writing bank for the pointer memory 31. At this point, if it is determined that branching is performed to the left side of the node, the classification module 50 writes the address of the learning data in ascending order of the address (from the start address (0)) in the bank B. If it is determined that branching is performed to the right side of the node, the classification module 50 writes the address of the learning data in descending order of the address (from the end address (mid_address_1_0)) in the bank B. The classification module 50 then returns, to the address manager 12, an address (intermediate address) in the bank B corresponding to a boundary between the address of the learning data branched to the left side and the address of the learning data branched to the right side. The intermediate address is used for the next branch processing.

The address calculator 121 calculates two start addresses and two end addresses corresponding to the next two nodes using the expression (23) described above based on the node address 0 of the present node (depth 2, node 0) received from the control unit 11, the intermediate address received from the classification module 50, and the start address and the end address of the present node. Specifically, the address calculator 121 calculates the start address and the end address at depth 3, node 0, and the start address and the end address at depth 3, node 1. The address calculator 121 then transmits, to the address storage destination control unit 122, the calculated addresses and the storage addresses (node addresses 0, 1) indicating storage destinations of the addresses.

The address storage destination control unit 122 stores the respective addresses calculated by the address calculator 121 in storage regions indicated by the storage addresses (node addresses 0, 1) in the start address memory 123B_ST for the bank B and the end address memory 123B_ED for the bank B corresponding to the bank B designated by the selection signal received from the control unit 11. Specifically, the address storage destination control unit 122 stores the start address (0) in the bank B corresponding to depth 3, node 0 at the node address 0 in the start address memory 123B_ST for the bank B, and stores the end address (mid_address_2_0) in the bank B corresponding to depth 3, node 0 at the node address 0 in the end address memory 123A_ED for the bank B. Furthermore, the address storage destination control unit 122 stores the start address (mid_address_2_0+1) in the bank B corresponding to depth 3, node 1 at the node address 1 in the start address memory 123B_ST for the bank B, and stores the end address (mid_address_1_0) in the bank B corresponding to depth 3, node 1 at the node address 1 in the end address memory 123B_ED for the bank B.

The processing is repeatedly performed in accordance with procedures illustrated in FIG. 34 to FIG. 37 as described above.

Configuration of Learning and Discrimination Device for Data Parallel

FIG. 38 is a diagram illustrating an example of a module configuration for implementing Data Parallel for the learning and discrimination device according to the third embodiment. The following describes a module configuration of a learning and discrimination device 1 c (an example of a learning device) according to the present embodiment for implementing Data Parallel with reference to FIG. 38 . In the configuration illustrated in FIG. 38 , the number of division for Data Parallel is assumed to be 2, but the number of division is not limited thereto.

To implement Data Parallel for the sample data (the learning data or the discrimination data), the data memory is divided into the two data memories 30 a and 30 b (data memories) to hold divided pieces of sample data as illustrated in FIG. 38 . Although not illustrated in the data memory 30 b of FIG. 38 , the data memory 30 b also includes the pointer memory 31, the feature memory 32, and the state memory 33 similarly to the data memory 30 a. However, it is not sufficient to simply divide the memory that holds the sample data, and a mechanism for performing processing (learning processing, discrimination processing, and the like) on the divided pieces of sample data in parallel is required. In the example illustrated in FIG. 38 , the number of arranged modules that perform discrimination processing is the same as that of the divided data memories. That is, the learning and discrimination device 1 c includes the classification modules 50 a and 50 b (discriminating units) for performing discrimination processing on respective pieces of sample data stored in the two data memories 30 a and 30 b in parallel.

In a case of implementing Data Parallel, as described above, there is provided the address manager 12 configured by hard logic for each division. Specifically, as illustrated in FIG. 38 , the learning and discrimination device 1 c for implementing Data Parallel includes a control module 15 a including address managers 12 a and 12 b (managers) each serving as the address manager 12 corresponding to each division. The control module 15 a includes the CPU 10 including the control unit 11, and the address managers 12 a and 12 b.

The address manager 12 a corresponds to the data memory 30 a and the classification module 50 a, and performs address management for the banks A and B in the pointer memory 31 of the data memory 30 a. The address manager 12 b corresponds to the data memory 30 b and the classification module 50 b, and performs address management for the banks A and B in the pointer memory 31 of the data memory 30 b. Even when the number of division is equal to or larger than 3, the address manager 12 may be similarly provided for each division.

Configuration for Simply Explaining Function of Address Manager for Data Parallel

FIG. 39 is a diagram illustrating a configuration for explaining a function of the address manager in a case of implementing Data Parallel for the learning and discrimination device according to the third embodiment. The following describes a configuration simply representing a function of the address manager 12 for Data Parallel with reference to FIG. 39 . To give more generalized description, the number of division is assumed to be N in FIG. 39 .

As illustrated in FIG. 39 , a control module 15 b of the learning and discrimination device that implements the number of division N includes the control unit 11, and address managers 12_1, 12_2, . . . , and 12_N. A learning unit 100_1 is comprehensively illustrated as a module having a learning function for the data memory 30 corresponding to the first division, the classification module 50, and the data memory 30 of the learning module 20. The address manager 12_1 calculates and transmits, to the learning unit 100_1, the start address and the end address for reading and writing the address from/into the bank. The address manager 12_1 then receives the intermediate address calculated by the classification module 50 of the learning unit 100_1, and calculates the start address and the end address of the next node.

Similarly, the address managers 12_2, . . . , and 12_N respectively provides, to learning units 100_2, . . . , and 100_N, a function similar to the function provided to the learning unit 100_1 of the address manager 12_1 described above.

As described above, in the present embodiment, in a case of learning the learning data at the node by the GBDT by Data Parallel, that is, in a case of dividing the learning data into pieces to be learned in parallel, the address managers 12 are provided corresponding to the number of division, and the corresponding address manager 12 performs address management used for learning and discrimination of the learning data stored in each data memory 30. Due to this, the number of clocks required for address calculation becomes the same as that in a case in which the number of division is 1, and the speed of address calculation for the learning data is greatly increased. For example, in a case in which the number of division is 100, the time required for address calculation is 1/100 of that in a case in which address calculation is sequentially performed.

Fourth Embodiment

The following describes the learning and discrimination device according to a fourth embodiment, mainly about differences from the learning and discrimination device according to the second embodiment. The present embodiment describes a configuration of dividing the model memory for each division for Data Parallel, and performing processing of calculating the index value representing recognition performance for each division.

Entire Configuration of Learning and Discrimination Device

FIG. 40 is a diagram illustrating an example of a module configuration of the learning and discrimination device according to the fourth embodiment to which Data Parallel is applied. With reference to FIG. 40 , the following describes a module configuration of a learning and discrimination device 1 d (an example of a learning device) according to the present embodiment. In the configuration illustrated in FIG. 40 , the number of division for Data Parallel is assumed to be 2, but the number of division is not limited thereto.

To implement Data Parallel for the sample data (the learning data or the discrimination data), first, the data memory is divided into two data memories 30 a and 30 b (data memories) to hold divided pieces of sample data as illustrated in FIG. 40 , similarly to the learning and discrimination device 1 a illustrated in FIG. 16 described above. Although not illustrated in the data memory 30 b of FIG. 40 , the data memory 30 b also includes the pointer memory 31, the feature memory 32, and the state memory 33 similarly to the data memory 30 a. However, it is not sufficient to simply divide the memory that holds the sample data, and a mechanism for performing processing (learning processing, discrimination processing, and the like) on the divided pieces of sample data in parallel is required. In the example illustrated in FIG. 40 , the number of arranged modules that perform discrimination processing is the same as that of the divided data memories. That is, the learning and discrimination device 1 d includes classification modules 50 a and 50 b (discriminating units) for performing discrimination processing on respective pieces of sample data stored in the two data memories 30 a and 30 b in parallel.

The learning and discrimination device 1 d further includes two model memories 40 a and 40 b (model memories) the number of which is equal to the number of division for Data Parallel so that each of the classification modules 50 a and 50 b can independently read out the node data. In this case, the classification modules 50 a and 50 b need to use the same node data of the decision tree (model) for the discrimination processing and update processing for a sample weight (described later). Thus, the learning module 20 is assumed to write the same node data obtained through the learning processing into the respective model memories 40 a and 40 b. As illustrated in FIG. 40 , the learning module 20 included in the learning and discrimination device 1 d may be the learning module 20 a illustrated in FIG. 21 described above, or the learning module 20 b illustrated in FIG. 25 .

The classification modules 50 a and 50 b of the learning and discrimination device 1 d according to the present embodiment calculates an Area Under the Curve (AUC) as an index value indicating recognition performance of the decision tree (model) learned by the learning module 20, and transmits the AUC to the control unit 11. That is, the classification module 50 a calculates the AUC from the sample weight (described later) and the like corresponding to the learning data related to division that is stored in the data memory 30 a, and transmits the AUC to the control unit 11. The classification module 50 b calculates the AUC from the sample weight (described later) and the like corresponding to the learning data related to division that is stored in the data memory 30 b, and transmits the AUC to the control unit 11. Specific configurations of the classification modules 50 a and 50 b for calculating the AUC will be described later.

Configuration of AUC Calculator in Learning and Discrimination Device

FIG. 41 is a diagram illustrating a configuration in a case in which the number of AUC calculators is assumed to be 1 for Data Parallel. FIG. 42 is a diagram illustrating a configuration of including the AUC calculator for each division for Data Parallel. With reference to FIG. 41 and FIG. 42 , the following describes the configuration of the AUC calculator for Data Parallel.

The classification modules 50 a and 50 b update the sample weight and the gradient information for each piece of the learning data every time learning of the decision tree performed by the learning module 20 ends. In this case, the sample weight is a sum total of leaf weight of a leaf at a branch destination as a result of branching of a corresponding piece of learning data in each decision tree that has been learned. The classification modules 50 a and 50 b calculate the AUC as an index value of recognition performance of the decision tree that has been learned up to this point using the updated sample weight. The AUC calculated by the classification modules 50 a and 50 b is used for performing early stopping, for example. In this case, early stopping is a method of interrupting the learning processing at the time when improvement in recognition performance of data for evaluation (discrimination data) is stopped, which is a method typically used in a field of machine learning. In this way, by interrupting the learning processing by early stopping, the learning processing can be prevented from being unnecessarily continued, and the learning processing can be interrupted before overlearning proceeds. The index value of recognition performance of the decision tree calculated by the classification modules 50 a and 50 b is not limited to the AUC, and another index value for recognition performance may be calculated. In the present embodiment, it is assumed that the AUC is calculated as the index value of recognition performance of the decision tree hereinafter.

In a configuration for Data Parallel, as described above, the speed of learning processing is increased by dividing the learning data. In calculation processing for the AUC as an index value of recognition performance of the learned decision tree, basically, it is required to compare sample weights and labels of all pieces of the learning data, and processing time is prolonged in proportion to the number of pieces of learning data, which may become a bottleneck in increasing the speed of processing in Data Parallel. The label indicates correct data defined by each piece of the learning data.

FIG. 41 illustrates a configuration of including one AUC calculator 81 that calculates the AUC using the sample weights of all pieces of the learning data in Data Parallel. The learning unit 100_1 illustrated in FIG. 41 is comprehensively illustrated as a module having a learning function for the data memory 30 a corresponding to the first division, the classification module 50 a, and the data memory 30 a of the learning module 20. The learning unit 100_2 is comprehensively illustrated as a module having a learning function for the data memory 30 b corresponding to the second division, the classification module 50 b, and the data memory 30 b of the learning module 20. The AUC calculator 81 receives the learning data related to each division, that is, the sample weights of all pieces of the learning data from the learning units 100_1 and 100_2, and calculates the AUC. In a case of the configuration illustrated in FIG. 41 , the processing time for learning is shortened by dividing the learning data into pieces to be learned in parallel by Data Parallel, but the AUC is calculated by using the sample weights of all pieces of the learning data. Accordingly, the processing time for calculation is prolonged in proportion to the number of pieces of the learning data.

Thus, the learning and discrimination device 1 d according to the present embodiment includes the AUC calculator for each division. The example illustrated in FIG. 42 is a configuration in a case in which the number of division is 2, and AUC calculators 81 a and 81 b (performance calculators) respectively corresponding to the learning units 100_1 and 100_2 are provided. Due to this, the AUC calculators 81 a and 81 b calculate the AUC in parallel using the sample weights of respective divided pieces of the learning data, so that it is not required to calculate the AUC by the entire AUC calculators 81 a and 81 b, and the speed of the calculation processing for the AUC can be increased. Next, with reference to FIG. 43 , the following describes a specific configuration of the learning and discrimination device 1 d including the AUC calculators 81 a and 81 b.

FIG. 43 is a diagram illustrating a configuration of a principal part of the learning and discrimination device according to the fourth embodiment. As illustrated in FIG. 43 , the classification module 50 a includes the AUC calculator 81 a described above, a sample weight update unit 82 a, and a gradient information update unit 83 a. The classification module 50 b includes the AUC calculator 81 b described above, a sample weight update unit 82 b, and a gradient information update unit 83 b. The control unit 11 includes a determiner 13.

The sample weight update unit 82 a is a module that updates the sample weight for each piece of the learning data related to division that is stored in the data memory 30 a every time learning of one decision tree performed by the learning module 20 ends. Specifically, the sample weight update unit 82 a updates the sample weight for each piece of the learning data related to division by using the following expression (24).

$\begin{matrix} {{\hat{y}}_{i}^{(t)} = {{\sum\limits_{k = 1}^{t}{f_{k}\left( x_{i} \right)}} = {{\hat{y}}_{i}^{({t - 1})} + {f_{t}\left( x_{i} \right)}}}} & (24) \end{matrix}$

The expression (24) is the same as the fourth expression in the expression (8) described above. As represented by the expression (24), the sample weight of the i-th learning data is a sum total of the leaf weight of the leaf branching in each decision tree that has been learned. The first term of the right side of the expression (24) represents the sample weight up to this point, and the second term represents the leaf weight of the target learning data in the decision tree that is currently learned. Branching in each decision tree that has been learned is performed similarly to the configuration and the operation of the classification module 50 illustrated in FIG. 15 described above. That is, the sample weight update unit 82 a reads the feature amount from the data memory 30 a to be compared with node data read from the model memory 40 a for each node of the decision tree. As a result of comparison, in accordance with a node lower than the present node to which the learning data branches, the sample weight update unit 82 a reads out, from the model memory 40 a, the node data of the node to which the learning data branches. Thus, the sample weight update unit 82 a needs to read the node data from the model memory 40 a multiple times corresponding to the depth of the decision tree for each piece of the learning data. The sample weight update unit 82 a updates an original sample weight stored in the data memory 30 a with the calculated sample weight.

The gradient information update unit 83 a is a module that calculates and updates gradient information (a first-order gradient g_(i), a second-order gradient h_(i)) by the expression (11) described above using the sample weight updated by the sample weight update unit 82 a. In the expression (11), 1 is an optional loss function. For example, in a case of a cross entropy error function, the gradient information can be calculated by the following expression (25).

$\begin{matrix} {{g_{i} = {{\frac{1}{1 + e^{- {\hat{y}}_{i}}} - y_{i}} = {p_{i} - y_{i}}}}{h_{i} = {\frac{1 + e^{- {\hat{y}}_{i}}}{\left( {1 + e^{- {\hat{y}}_{i}}} \right)^{2}} = {p_{i}\left( {1 - p_{i}} \right)}}}} & (25) \end{matrix}$

In the expression (25), pi is a value obtained by normalizing the first term of the right side of the expression (24) to be 0-1 using a sigmoid function. The gradient information update unit 83 a updates the original gradient information stored in the data memory 30 a with the calculated gradient information.

The AUC calculator 81 a is a module that calculates the AUC by using the label of the learning data read out from the data memory 30 a and the sample weight calculated by the sample weight update unit 82 a. The AUC calculator 81 a outputs the calculated AUC to the determiner 13 of the control unit 11.

The sample weight update unit 82 b is a module that updates the sample weight of each piece of the learning data related to division that is stored in the data memory 30 b every time learning of one decision tree performed by the learning module 20 ends. A specific method of calculating the sample weight by the sample weight update unit 82 b is the same as the processing performed by the sample weight update unit 82 a described above.

The gradient information update unit 83 b is a module that calculates and updates the gradient information (a first-order gradient g_(i), a second-order gradient h_(i)) by the expression (11) described above using the sample weight updated by the sample weight update unit 82 b. A specific method of calculating the gradient information by the gradient information update unit 83 b is the same as the processing performed by the sample weight update unit 82 b described above.

The AUC calculator 81 b is a module that calculates the AUC by using the label of the learning data read out from the data memory 30 b and the sample weight calculated by the sample weight update unit 82 b. The AUC calculator 81 b outputs the calculated AUC to the determiner 13 of the control unit 11.

In this case, the AUC calculated by using all the pieces of learning data is not necessarily equal to the AUC that is calculated by each of the AUC calculators 81 a and 81 b using the learning data related to each division. If a set of the learning data for calculating the AUC is changed, the AUC typically becomes a different value. However, in a case of using the AUC as an index value for interrupting the learning processing by early stopping described above, it is sufficient to find whether the AUC is improved, so that the AUC is not required to be strictly calculated by using all the pieces of learning data.

The determiner 13 is a module that determines whether to perform early stopping on the learning processing for the decision tree performed by the learning module 20 based on the respective AUCs calculated by the AUC calculators 81 a and 81 b. For example, if it is determined that any one of the AUCs calculated by the AUC calculators 81 a and 81 b, or an average value, a total value, or the like of both AUCs is stabilized to be a value larger than a predetermined value, the determiner 13 determines to perform early stopping. As a criterion for determining whether the AUC is stabilized, for example, when a state in which the AUC is larger than the predetermined value continues over a predetermined number of rounds, the determiner 13 may determine to perform early stopping. As a specific method for early stopping, for example, initialization on the pointer memory 31 may be stopped in a case of newly performing learning of the decision tree by the control unit 11, and an output of a trigger to the learning module 20 and the classification modules 50 a and 50 b may be stopped.

The control unit 11 is assumed to include the determiner 13, but does not necessarily include the determiner 13. In this case, the configuration may be such that the AUC calculated by the AUC calculators 81 a and 81 b may be output to the outside, for example. The configuration may also be such that each of the classification modules 50 a and 50 b includes a module corresponding to the determiner 13 instead of a configuration in which the control unit 11 includes the determiner 13, and when the module determines whether to perform early stopping, the module transmits a determination result thereof to the control unit 11.

All of the AUC calculators 81 a and 81 b, the sample weight update units 82 a and 82 b, and the gradient information update units 83 a and 83 b are not necessarily configured as hardware modules.

For example, the sample weight update units 82 a and 82 b, and the gradient information update units 83 a and 83 b are not necessarily present as independent modules in the classification modules 50 a and 50 b. That is, the classification modules 50 a and 50 b may be configured to have the functions of the sample weight update units 82 a and 82 b and the gradient information update units 83 a and 83 b as a whole.

Effect of Including AUC Calculator for Each Division

FIG. 44 is a diagram illustrating an example of a comparison result of processing time between a case in which one AUC calculator is provided and a case in which the AUC calculator is provided for each division. With reference to FIG. 44 , the following describes the comparison result of processing time for calculating the AUC between the case in which one AUC calculator is provided and the case in which the AUC calculator is provided for each division.

For example, it is assumed that the number of division is 2, and the learning data is equally divided into pieces for the data memories 30 a and 30 b. In this case, in a case of including the AUC calculator for each division, that is, in a case of calculating the AUC for each division as illustrated at (b) in FIG. 44 , time for calculating the AUC can be reduced and the processing speed can be increased as compared with the case of including one AUC calculator as illustrated at (a) in FIG. 44 , that is, the case in which the AUC is calculated for all pieces of the learning data at a time.

In this case, the AUC calculated by using all pieces of the learning data is not necessarily equal to the AUC calculated by using a piece of the learning data for each division. If a set of the learning data for calculating the AUC is changed, the AUC typically becomes a different value. However, in a case of using the AUC as an index for early stopping, it is sufficient to determine whether the AUC is improved, so that the AUC is not required to be strictly calculated by using all pieces of the learning data. As described above, it is sufficient that the determiner 13 can determine whether to perform early stopping based on any one of the AUCs calculated by the AUC calculators 81 a and 81 b, or an average value, a total value, or the like of both AUCs. In this way, by interrupting the learning processing by early stopping, the learning processing can be prevented from being unnecessarily continued, and the learning processing can be interrupted before overlearning proceeds.

As described above, in the learning and discrimination device 1 d according to the present embodiment, the number of division for Data Parallel is not limited to 2, and may be equal to or larger than 3. In this case, it is sufficient to include the AUC calculator for each division, and the processing time for the calculation processing for the AUC can be reduced to be “1/the number of division” as compared with the case of including one AUC calculator.

Effect of Including Model Memory for Each Division

FIG. 45 is a diagram illustrating an example of a comparison result of processing time between a case in which one model memory is provided and a case in which the model memory is provided for each division. With reference to FIG. 45 , the following describes a comparison result of processing time for processing of accessing the model memory between the case in which one model memory is provided and the case in which the model memory is provided for each division.

As described above, the sample weight update units 82 a and 82 b refer to the node data in the model memories 40 a and 40 b at the time of update processing for the sample weight corresponding to the learning data. If the state is Data Parallel in which the learning data is divided into a plurality of pieces and there is only one model memory, the model memory cannot be accessed for each division at the time of update processing for the sample weight, and waiting time is generated for each piece of the learning data. For example, in a case in which the number of division is 3 and there is one model memory (model memory 40), the model memory 40 cannot be independently accessed for each division. As illustrated at (a) in FIG. 45 , the model memory 40 needs to be accessed in series (successively).

On the other hand, in a case of including the model memory (model memories 40 a and 40 b) for each division like the learning and discrimination device 1 d illustrated in FIG. 40 described above, the model memory can be accessed in parallel for each division at the time of update processing for the sample weight. For example, in a case in which the number of division is 3 and the model memory is provided for each division (model memories 40 a to 40 c), as illustrated at (b) in FIG. 45 , the model memory (model memories 40 a to 40 c) can be accessed in parallel for each division, so that the processing speed can be increased. In this way, the configuration of including the model memory for each division can accelerate the processing time for the learning processing.

Fifth Embodiment

The present embodiment describes an operation in a case in which the sample data and the like are stored in an external memory, not in the SRAM inside a processing chip, as a data memory.

As described above, the data memory (data memory 30 and the like) included in the learning and discrimination device is assumed to be the SRAM inside the processing chip that enables random access. However, data capacity of the SRAM as a data memory inside the processing chip is limited, so that the SRAM cannot handle learning processing with large-scale sample data (learning data). The present embodiment describes a configuration of learning the decision tree at high speed in a case of using, as a data memory, a dynamic random access memory (DRAM) having large capacity that is arranged outside the processing chip.

FIG. 46 is a diagram illustrating an example of the entire configuration of the learning and discrimination device according to a fifth embodiment. FIG. 47 is a diagram illustrating an example of a module configuration of one learning unit of the learning and discrimination device according to the fifth embodiment. FIG. 48 is a diagram illustrating an example of a mode of storing the sample data in an external memory of the learning and discrimination device according to the fifth embodiment. The following describes a configuration and an operation of a learning and discrimination device 1 e according to the present embodiment with reference to FIG. 46 to FIG. 48 . The learning and discrimination device 1 e according to the present embodiment is assumed to have a configuration in a case in which the number of division for Data Parallel is 3.

As illustrated in FIG. 46 , the learning and discrimination device 1 e according to the present embodiment includes a distributing unit 401, First-In First-Out (FIFO) units 402_1 to 402_3, learning units 100_1 to 100_3, FIFO units 403_1 to 403_3, a left buffer unit 404L (first buffer unit), a right buffer unit 404R (second buffer unit), and data memories 30D (data storage units). The learning and discrimination device 1 e further includes the CPU 10 as illustrated in FIG. 47 . In FIG. 46 , for simplifying the description, the data memories 30D are arranged on the left and the right, but is basically a single memory. Depending on a configuration, the left and right data memories 30D may be a plurality of different memories because speedup is enabled due to concurrent access. The learning and discrimination device 1 e may include other constituent elements, for example, a RAM serving as a work area of the CPU 10, a ROM storing a computer program and the like executed by the CPU 10, an auxiliary storage device storing various kinds of data (computer program and the like), and a communication I/F that communicates with an external device in addition to the constituent elements illustrated in FIG. 46 .

The data memory 30D is a memory that stores sample data (including the learning data and the discrimination data) and the state information (w, g, h), and constituted of a DRAM. The data memory 30D stores, for example, the sample data and the state information in a mode illustrated in FIG. 48 . FIG. 48 illustrates, as an example, an initial mode of storing the sample data and the state information in a case in which the number of feature amounts of the sample data is 8, a bit length of each feature amount is 8 bits, and a bit length of the state information with respect to each piece of the sample data is 32 bits. That is, in the initial state, the feature amounts and the state information are stored in this order, in order of the address, and in an ascending order of the number of sample data. As described above, the data memory 30D is implemented by the DRAM, so that reading and writing are not performed on the data memory 30D for each address but are performed assuming continuous addresses as a block. Due to this, the processing speed can be increased as compared with a case of making access for each single address.

For example, in a case in which the processing speed is assumed to be the highest when the data memory 30D makes access in units of 16 bytes, the processing speed becomes the highest when access is made in units of a row in FIG. 48 . In this case, as described later, the distributing unit 401 performs reading-out for each row (assuming that each row is 1 block) from the data memory 30D, and the sample data and the state information are distributed to the respective learning units (learning units 100_1 to 100_3) for each data number of the sample data included in the read-out row. Each learning unit performs learning for each node of the decision tree, and derives a branch condition under which the branch score is the largest.

As illustrated in FIG. 47 , the data memory 30D includes a bank a (bank region), and a bank b (bank region). An operation of reading and writing the data from/into the bank a and the bank b is equivalent to an operation of reading and writing the data from/into the bank A and the bank B of the pointer memory 31 described above. However, unlike the bank A and the bank B, the storage address of the sample data is not stored in the bank a and the bank b but the sample data and the state information themselves are stored therein. Thus, the data memory 30D does not include the pointer memory 31 that manages the storage address of the sample data. Similarly to the case of the bank A and the bank B, a bank from which the data is read out of the bank a and the bank b is referred to as a read-out bank (bank region for reading-out), and a bank into which the data is written is referred to as a writing bank (bank region for writing). In the following description, the sample data is assumed to be the learning data used for learning the decision tree.

The distributing unit 401 is a module that reads out the sample data and the state information for each block from the bank a or the bank b of the data memory 30D, and distributes the sample data and the state information to the respective learning units (learning units 100_1 to 100_3) for each data number of the sample data included in the block. In this way, by reading out the data from the data memory 30D in units of a block, sufficient speed of the data memory 30D as an external memory can be achieved.

The FIFO units 402_1 to 402_3 are modules that buffer the sample data and the state information distributed from the distributing unit 401 in a FIFO format, and output the sample data and the state information at a timing of processing performed by each of the learning units 100_1 to 100_3.

As illustrated in FIG. 47 , the learning unit 100_1 is comprehensively illustrated as a module having a learning function for the learning module 20, the classification module 50, and the model memory 40 corresponding to the first division. Similarly, the learning unit 100_2 corresponds to the second division, and the learning unit 100_3 corresponds to the third division. The operations of the learning module 20, the classification module 50, and the model memory 40 are described above. For example, in a case of causing the sample data at the node corresponding to the branch condition to branch to the left and the right based on the branch condition derived by the learning module 20, the classification module 50 reads out the data from the data memory 30D via the FIFO units 402_1 to 402_3 again, causes the sample data to branch under the branch condition, and writes the branched sample data and state information into the other bank (writing bank) different from the bank (read-out bank) at the time of reading-out via the left buffer unit 404L and the right buffer unit 404R (described later).

In FIG. 47 , the learning units 100_1 to 100_3 are collectively referred to as the “learning unit 100”, and for simplifying the description, the distributing unit 401, the FIFO units 402_1 to 402_3, the FIFO units 403_1 to 403_3, the left buffer unit 404L, and the right buffer unit 404R are not illustrated. The learning module 20 may be included in the learning unit 100 for each division for Data Parallel, or may correspond to an internal configuration of performing processing for each division for Data Parallel like the learning modules 20 a and 20 b described above. The classification module 50 may be included in the learning unit 100 for each division for Data Parallel as illustrated in FIG. 16 or FIG. 38 described above, for example. For example, the model memory 40 included in the learning unit 100 may be the same for each division for Data Parallel as illustrated in FIG. 16 or FIG. 38 described above, or may be included therein for each division for Data Parallel as illustrated in FIG. 40 .

As illustrated in FIG. 47 , the model memory 40 is not an external memory unlike the data memory 30D. This is because the data capacity required for the model memory 40 is small, and random access is indispensable at the time of discrimination processing performed by the classification module 50, so that reading and writing speed becomes very low with an external memory such as a DRAM. Thus, the model memory 40 is preferably constituted of an SRAM inside the processing chip.

The FIFO units 403_1 to 403_3 are modules that buffer, in a FIFO format, the sample data the branching direction of which at the node as the learning target is discriminated by the function of the classification module 50 of the learning units 100_1 to 100_3 and information about the branching direction as outputs of the learning units 100_1 to 100_3. The FIFO units 403_1 to 403_3 appropriately output the buffered sample data to the left buffer unit 404L or the right buffer unit 404R in a FIFO format in accordance with information about a corresponding branching direction.

In this way, by arranging the FIFO units 402_1 to 402_3 described above on an input side of the learning units 100_1 to 100_3 and arranging the FIFO units 403_1 to 403_3 on an output side thereof, an operating frequency of the learning units 100_1 to 100_3 (an engine clock region illustrated in FIG. 46 ) can be separated from an operating frequency of the modules other than the learning units 100_1 to 100_3 (the data memory 30D, the distributing unit 401, the left buffer unit 404L, and the right buffer unit 404R) (a memory clock region illustrated in FIG. 46 ). Due to this, the operating frequency in the memory clock region can be maximized, and sufficient speed of reading and writing for the data memory 30D can be achieved. Due to this, the processing by the learning units 100_1 to 100_3 and the reading and writing processing for each block on the data memory 30D can be performed in parallel, and the processing can be continued without stalling the processing performed by the learning units 100_1 to 100_3.

The left buffer unit 404L is a module that receives the sample data branched to the left of the node as a processing target from the FIFO units 403_1 to 403_3, and buffers the sample data in order on a time-series basis. The left buffer unit 404L includes an address counter and a data number counter (not illustrated). Each of the address counter and the data number counter increment count (+1) every time the sample data branched to the left is input to the left buffer unit 404L. When the data number counter indicates that the sample data having predetermined data capacity is buffered, the left buffer unit 404L writes the sample data having the data capacity into one of the bank a and the bank b, which is the writing bank, for each block in ascending order of the address utilizing the address indicated by the address counter. After writing all pieces of the buffered sample data into the writing bank, the left buffer unit 404L resets the data number counter.

The right buffer unit 404R is a module that receives the sample data branched to the right of the node as a processing target from the FIFO units 403_1 to 403_3, and buffers the sample data in order on a time-series basis. The right buffer unit 404R includes an address counter and a data number counter (not illustrated). The data number counter increments count (+1) every time the sample data branched to the right is input to the right buffer unit 404R. The address counter decrements count (−1) every time the sample data branched to the right is input to the right buffer unit 404R. When the data number counter indicates that the sample data having predetermined data capacity is buffered, the right buffer unit 404R writes the sample data having the data capacity into one of the bank a and the bank b, which is the writing bank, for each block in descending order of the address utilizing the address indicated by the address counter. That is, the sampling data buffered in the right buffer unit 404R is written into the writing bank by Last-In First-Out (LIFO). After writing all pieces of the buffered sample data into the writing bank, the right buffer unit 404R resets the data number counter.

In this case, assuming that the right buffer unit 404R also writes the sample data into the writing bank in ascending order of the address, if all pieces of the sample data branch to the left of the node, memory capacity corresponding to the number of all pieces of the sample data is required for the writing bank. The same applies to the left buffer unit 404L. Thus, in this case, the sum total of the capacity for writing the sample data by the left buffer unit 404L and capacity for writing the sample data by the right buffer unit 404R needs to be twice the memory capacity corresponding to the number of all pieces of the sample data. However, in the present embodiment, similarly to the operation of storing the address in the writing bank of the bank A and the bank B in the pointer memory 31 described above, the sample data branched to the left of the node that is output from the left buffer unit 404L is written into the writing bank of the bank a and the bank b in ascending order of the address, and the sample data branched to the right of the node that is output from the right buffer unit 404R is written into the writing bank in descending order of the address. Due to this, it is sufficient that the writing bank, that is, each of the bank a and bank b needs to have memory capacity corresponding to the number of all pieces of the sample data.

The predetermined data capacity as a basis of the timing at which the left buffer unit 404L and the right buffer unit 404R write the data into the bank a or the bank b of the data memory 30D is optimum capacity with which writing is efficiently performed on the data memory 30D. For example, the predetermined data capacity is capacity corresponding to a burst length of the data memory 30D to be used (for example, an integral multiple of (bit width)×(burst length) of the data memory 30D and the like). Basically, the buffer for a bit width corresponding to one address of a physical memory is required at the very least. For example, writing needs to be performed in units of 128 bytes at the minimum on a physical memory having 1024-bit width per one address. On top of that, it is preferable to have a buffer corresponding to the number of addresses for burst reading/writing corresponding to the data memory 30D, and perform writing in units of the buffer. For example, it is efficient that writing is performed in units of 128 bytes×4=512 bytes on a memory having 1024-bit width per one address and the burst length of 4. That is, writing may be performed in a case in which the sample data corresponding to the block described above is accumulated. In a case of performing reading-out/writing on the same memory (data memory 30D), there is overhead for switching thereof. Accordingly, the overhead can be reduced as a unit of reading-out/writing is large, but in this case, a large buffer size is required for the left buffer unit 404L and the right buffer unit 404R. Thus, for example, assuming that reading and writing are switched per 16 times of one burst access, reading-out and writing may be switched in units of 512 bytes×16=8192 bytes.

As the predetermined data capacity, for example, a fixed value determined in advance may be set as a threshold of the data number counter of the left buffer unit 404L and the right buffer unit 404R. Alternatively, as the predetermined data capacity, for example, a set value selected by the CPU 10 and the like among some set values determined in advance may be set as a threshold. In this case, a timing of selecting any one of the set values determined in advance may be when an operation of learning processing performed by the learning and discrimination device 1 e is stopped, or the set value may be dynamically selected during the operation of learning processing. In a case in which (predetermined data capacity) (capacity of the block) is satisfied, writing is enabled to be efficiently performed for each block.

In this way, with the learning and discrimination device 1 e according to the present embodiment, at the time of learning and discriminating the decision tree, information such as the sample data that is caused to branch in real time is not required to be written into the data memory 30D in units of the sample data at all times. It is sufficient that the sample data is reflected in units of a node and in units of a step similarly to the processing step described above with reference to FIG. 5 to FIG. 13 , and it is possible to take a measure of putting writing performed by the data memory 30D on the writing bank on standby until the sample data is accumulated up to efficient data capacity in the left buffer unit 404L and the right buffer unit 404R. In this way, when the sample data is accumulated up to certain data capacity and reading/writing is performed in units of a certain size (block), finely divided random access can be prevented, and sufficient speed of the data memory 30D as an external memory can be achieved.

For example, the address manager (12 a, 12 b, . . . ) illustrated in FIG. 38 described above may perform address management for reading out the sample data from the read-out bank of the data memory 30D by the distributing unit 401, and address management for writing the sample data into the writing bank of the data memory 30D from the left buffer unit 404L and the right buffer unit 404R, for each division for Data Parallel.

At the time of discrimination processing performed by the classification module 50, the classification module 50 is required to write the sample data branched at a target node into the data memory 30D while reading out the sample data from the data memory 30D. In this case, by dividing the operation of reading-out and writing to be used for one data memory 30D on a time-series basis, a reading/writing operation for the data memory 30D can be implemented. At this point, it takes a long time to switch between a reading-out mode and a writing mode for the data memory 30D in some cases, but this overhead can be reduced by switching the mode for each block, or switching the mode in a longer unit by increasing the capacity of the FIFO units 402_1 to 402_3, the FIFO units 403_1 to 403_3, the left buffer unit 404L, and the right buffer unit 404R. Specifically, the reading-out mode and the writing mode may be switched for each data amount with which efficiency of transferring the data to the data memory 30D is maximized. The embodiment is not limited to dividing reading-out and writing for one data memory 30D to be implemented on a time-series basis, and reading-out and writing may be independently implemented for the data memory of the bank a and the data memory of the bank b. Due to this, read-out processing for one bank and write processing for the other bank are enabled to be performed at the same time, and the processing is enabled to be performed at higher speed. The embodiment is not limited to switching between the reading-out mode and the writing mode for each data amount with which the transfer efficiency is maximized, and the switching may be performed for each data amount with which the transfer efficiency becomes equal to or larger than a predetermined value.

In the first to the fourth embodiments described above, the pointer memory 31 is deployed in the data memory 30, and the addresses of the sample data are stored in the banks A and B, so that it is sufficient that the capacity of the feature memory 32 and the state memory 33 is total capacity of the sample data corresponding to all the addresses that can be stored in any one of the banks A and B. However, at the time of reading out or writing the information of the sample data at each node, the addresses on the feature memory 32 and the state memory 33 that are stored in the banks A and B become discrete, so that random access is required, and access speed is reduced in a case of using the DRAM as the data memory 30. In contrast, in the present embodiment, two banks, that is, the banks a and b into which the sample data and the state information writing is performed without using the pointer memory 31. Accordingly, the data capacity is increased, but processing can be performed at high speed even when the DRAM as the data memory 30D is used because reading-out or writing of the sample data and the state information is performed in units of a block stored at the continuous addresses.

As described above, in the learning and discrimination device 1 e according to the present embodiment, the data (the sample data and the state information) is read or written from/into the data memory 30D as an external memory in units of a predetermined block, the left buffer unit 404L and the right buffer unit 404R buffer the sample data that is caused to branch at a specific node by the learning unit 100 up to volume determined in advance, and when the sample data is accumulated up to the volume, the sample data is written into the continuous addresses in the data memory 30D for each predetermined block. Due to this, the DRAM and the like can be employed as the data memory 30D, and speed of learning each decision tree can be increased for a large amount of sample data.

The learning and discrimination device 1 e according to the fifth embodiment described above is assumed to have a Data Parallel configuration in which the number of division is 3. Alternatively, the number of division may be any other number, or the number of division may be 1, that is, a configuration other than Data Parallel may be employed.

Sixth Embodiment

The present embodiment describes a case in which, as a data memory in which the sample data and the like are stored, an external memory is used instead of the SRAM inside the processing chip, and an operation of selecting the sample data to be used for update processing for the gradient information and learning of the next decision tree by subsampling using the sample data stored in the external memory.

In learning by the gradient boosting decision tree (GBDT), data subsampling (hereinafter, in the present embodiment, simply referred to as “subsampling”) of randomly selecting and learning part of the sample data in learning of each decision tree is widely used for the purpose of improving recognition accuracy and shortening processing time. By performing subsampling before and after learning of the decision tree, sample data groups used for learning the respective decision trees are different, and variation of generated decision trees is widened, so that prediction accuracy can be improved and overlearning can be prevented from being generated. As described above in the first embodiment and the like, in a case of utilizing the SRAM inside the chip, subsampling is implemented by randomly selecting the sample data in accordance with a subsampling rate indicating a ratio of the sample data used for learning at the time of initializing the pointer memory 31 configured in the SRAM (data memory 30) at an initial step of learning of each decision tree.

As described above in the fifth embodiment, in a case of using the external memory (DRAM and the like) having large capacity that is arranged outside the processing chip, the pointer memory 31 described above in the first embodiment and the like is not used, so that subsampling is required to be implemented by another configuration. As such a method of implementing subsampling, for example, the following two methods are exemplified.

The first method is a method of storing the sample data subjected to subsampling in the SRAM inside the processing chip. This method can be utilized if data volume of the sample data subjected to subsampling can be fit into the SRAM inside the processing chip, but storage capacity of the SRAM is very small, so that this method is not a realistic idea in a case of handling a large amount of sample data.

The second method is a method of storing an address of the sample data subjected to subsampling in the SRAM inside the processing chip. This method is also hardly implemented in a case in which the data volume of the sample data is large. For example, the number of pieces of the sample data is 20000000 and the subsampling rate is 0.5, address space in which 10000000 pieces of sample data can be discriminated, that is, address space having the number of bits that can represent at least values of 0 to 9999999 is required, and the number of bits is represented as log₂(20000000×0.5). For example, an address with which eight pieces of sample data can be discriminated, that is, the number of bits with which values of 0 to 7 can be represented is log 2(8)=log₂(2³)=3 [bit]. In this case, log₂(20000000×0.5)≈23.25, so that data volume for storing addresses corresponding to all pieces of the sample data as the number of bits described above is represented as log₂(20000000×0.5)×20000000×0.5≈23.25×10000000=232.5 M[bit]. There are few FPGA including the SRAM having such data capacity therein. Reading cannot be performed at high speed unless a DRAM outside the processing chip is accessed by using continuous addresses as a block, so that high-speed learning cannot be implemented.

Thus, in the present embodiment, similarly to the fifth embodiment described above, subsampling is implemented by a configuration of storing the sample data in the DRAM outside the chip. In learning by the gradient boosting decision tree, gradients of all pieces of the sample data are required to be updated after learning of a certain decision tree is ended. In this update processing, the sample data (feature amount) and corresponding gradient information are required to be read from the DRAM outside the processing chip for each piece of the sample data, the gradient information is required to be updated, and the updated gradient information and the sample data are required to be written into the DRAM. At the time of writing the data into the DRAM, whether each piece of the sample data is utilized for learning of the next decision tree is determined based on the subsampling rate designated in advance, the sample data to be utilized and the sample data not to be utilized are stored in a prepared buffer, and at the time when pieces of the sample data having predetermined data volume are accumulated in a buffer, the pieces of sample data are written into the DRAM to implement subsampling. The following describes details about a configuration and an operation of the learning and discrimination device according to the present embodiment.

FIG. 49 is a diagram illustrating an example of the entire configuration of the learning and discrimination device according to a sixth embodiment. FIG. 50 is a diagram illustrating an example of a configuration of a subsampling unit of the learning and discrimination device according to the sixth embodiment. FIG. 51 is a diagram illustrating an example of a module configuration of one learning unit of the learning and discrimination device according to the sixth embodiment. The following describes a configuration and an operation (especially, a subsampling operation) of a learning and discrimination device if according to the present embodiment with reference to FIG. 49 to FIG. 51 . The description will be made assuming that the learning and discrimination device if according to the present embodiment has a configuration in a case in which the number of division for Data Parallel is 3. However, the number of division for Data Parallel is not limited to 3, and may be another number. Alternatively, the number of division may be 1, that is, a configuration that is not Data Parallel may be employed.

As illustrated in FIG. 49 , the learning and discrimination device if (an example of a learning device) according to the present embodiment includes the distributing unit 401, the First-In First-Out (FIFO) units 402_1 to 402_3, the learning units 100_1 to 100_3, the FIFO units 403_1 to 403_3, subsampling units 406_1 to 406_3, a use data buffer unit 405U (first buffer unit), a non-use data buffer unit 405N (second buffer unit), and the data memory 30D (data storage unit). The learning and discrimination device if further includes the CPU 10 as illustrated in FIG. 51 . In FIG. 49 , for simplifying the description, the data memories 30D are arranged on the left and the right, but is basically a single memory. Depending on a configuration, the left and right data memories 30D may be a plurality of different memories because speedup is enabled due to concurrent access. The learning and discrimination device if may include other constituent elements, for example, a RAM serving as a work area of the CPU 10, a ROM storing a computer program and the like executed by the CPU 10, an auxiliary storage device storing various kinds of data (computer program and the like), and a communication I/F that communicates with an external device in addition to the constituent elements illustrated in FIG. 49 .

The data memory 30D is a memory that stores sample data (including the learning data and the discrimination data) and the state information (w, g, h), and constituted of a DRAM. The data memory 30D stores, for example, the sample data and the state information in a mode illustrated in FIG. 48 described above. The data memory 30D is implemented by the DRAM, so that reading and writing are not performed on the data memory 30D for each address but are performed assuming continuous addresses as a block. Due to this, the processing speed can be increased as compared with a case of making access for each single address.

For example, in a case in which the processing speed is assumed to be the highest when the data memory 30D makes access in units of 16 bytes, the processing speed becomes the highest when access is made in units of a row in FIG. 48 . In this case, as described later, the distributing unit 401 performs reading-out for each row (assuming that each row is 1 block) from the data memory 30D, and the sample data and the state information are distributed to the respective learning units (learning units 100_1 to 100_3) for each data number of the sample data included in the read-out row. Each learning unit performs learning for each node of the decision tree, performs an operation of deriving a branch condition under which the branch score becomes the largest, and performs an operation of newly calculating the gradient information for each piece of the sample data after learning of one decision tree.

As illustrated in FIG. 51 , the data memory 30D includes a bank a (a first bank region or a second bank region) and a bank b (a second bank region or a first bank region). The bank a is a data region on the data memory 30D that stores the sample data to be used for learning of the next decision tree buffered in the use data buffer unit 405U. The bank b is a data region on the data memory 30D that stores the sample data not to be used for learning of the next decision tree buffered in the non-use data buffer unit 405N. Functions of the bank a and the bank b may be reversed. In the data memory 30D, a memory of the bank a and a memory of the bank b may be configured as physically different memories.

As described later, the configuration of the learning and discrimination device if illustrated in FIG. 49 can be used not only for the subsampling operation but also for normal learning processing for the decision tree. An operation of reading and writing the data from/into the bank a and the bank b in a case in which the learning and discrimination device if performs the learning processing is equivalent to an operation of reading and writing the data from/into the bank A and the bank B of the pointer memory 31 described above. However, unlike the bank A and the bank B, the storage address of the sample data is not stored in the bank a and the bank b but the sample data and the state information themselves are stored therein. Thus, the data memory 30D does not include a data region corresponding to the pointer memory 31 that manages the storage address of the sample data. In the following description, the sample data is assumed to be the learning data used for learning of the decision tree.

The distributing unit 401 is a module that reads out the sample data and the state information as a target from which the gradient information (the first-order gradient, the second-order gradient) is calculated for each block from the bank a or the bank b of the data memory 30D at the time of subsampling operation after learning of one decision tree, and distributes the sample data and the state information to the respective learning units (learning units 100_1 to 100_3) for each data number included in the block. In this way, by reading out the data from the data memory 30D in units of a block, sufficient speed of the data memory 30D as an external memory can be achieved. An operation in a case in which the learning units 100_1 to 100_3 perform the operation of deriving the branch condition (learning operation for the decision tree) is the same as that in the fifth embodiment described above.

The FIFO units 402_1 to 402_3 are modules that buffer the sample data and the state information distributed from the distributing unit 401 in a FIFO format, and output the sample data and the state information at a timing of processing performed by each of the learning units 100_1 to 100_3.

As illustrated in FIG. 47 , the learning unit 100_1 is comprehensively illustrated as a module having a learning function for the learning module 20, the classification module 50 (update unit), and the model memory 40 corresponding to the first division. Similarly, the learning unit 100_2 corresponds to the second division, and the learning unit 100_3 corresponds to the third division. The operations of the learning module 20, the classification module 50, and the model memory 40 are described above.

For example, at the time of subsampling operation after learning of one decision tree, the classification module 50 reads out the sample data and the state information used for learning of the decision tree from the data memory 30D via the FIFO units 402_1 to 402_3. The classification module 50 newly calculates the gradient information for each piece of the sample data to update the state information, and outputs the updated state information and the sample data to the FIFO units 403_1 to 403_3 to be written into the data memory 30D. The operation of the classification module 50 in a case of performing the operation of deriving the branch condition for the decision tree (learning operation for the decision tree) is the same as that in the fifth embodiment described above.

In FIG. 51 , the learning units 100_1 to 100_3 are collectively referred to as the “learning unit 100”, and for simplifying the description, the distributing unit 401, the FIFO units 402_1 to 402_3, the FIFO units 403_1 to 403_3, the subsampling units 406_1 to 406_3, the use data buffer unit 405U, and the non-use data buffer unit 405N are not illustrated. The learning module 20 may be included in the learning unit 100 for each division for Data Parallel, or may correspond to an internal configuration of performing processing for each division for Data Parallel like the learning modules 20 a and 20 b described above. The classification module 50 may be included in the learning unit 100 for each division for Data Parallel as illustrated in FIG. 16 or FIG. 38 described above, for example. For example, the model memory 40 included in the learning unit 100 may be the same for each division for Data Parallel as illustrated in FIG. 16 or FIG. 38 described above, or may be included therein for each division for Data Parallel as illustrated in FIG. 40 .

As illustrated in FIG. 51 , the model memory 40 is not an external memory unlike the data memory 30D. This is because the data capacity required for the model memory 40 is small, and random access is indispensable at the time of discrimination processing performed by the classification module 50, so that reading and writing speed becomes very low with an external memory such as the DRAM. Thus, the model memory 40 is preferably constituted of the SRAM inside the processing chip.

The FIFO units 403_1 to 403_3 are modules that buffer, in a FIFO format, the sample data and the state information the gradient information of which is updated as outputs of the learning units 100_1 to 100_3 after learning of one decision tree by the function of the classification module 50. The FIFO units 403_1 to 403_3 appropriately output the buffered sample data and the state information to the subsampling units 406_1 to 406_3 in a FIFO format. The operations of the FIFO units 403_1 to 403_3 in a case of performing the operation of deriving the branch condition for the decision tree (learning operation for the decision tree) are the same as those in the fifth embodiment described above.

In this way, by arranging the FIFO units 402_1 to 402_3 described above on an input side of the learning units 100_1 to 100_3 and arranging the FIFO units 403_1 to 403_3 on an output side thereof, an operating frequency of the learning units 100_1 to 100_3 (an engine clock region illustrated in FIG. 49 ) can be separated from an operating frequency of the modules other than the learning units 100_1 to 100_3 (the data memory 30D, the distributing unit 401, the subsampling units 406_1 to 406_3, the use data buffer unit 405U, and the non-use data buffer unit 405N) (a memory clock region illustrated in FIG. 49 ). Due to this, the operating frequency in the memory clock region can be maximized, and sufficient speed of reading and writing for the data memory 30D can be achieved. Due to this, the processing by the learning units 100_1 to 100_3 and the reading and writing processing for each block on the data memory 30D can be performed in parallel, and the processing can be continued without stalling the processing performed by the learning units 100_1 to 100_3.

The subsampling units 406_1 to 406_3 are modules that determine whether to use the sample data and the state information including the updated gradient information output from the learning units 100_1 to 100_3 for learning of the next decision tree based on a subsampling rate designated in advance after learning of one decision tree, output the state information and the sample data to the use data buffer unit 405U in a case in which it is determined that they are used, and output the state information and the sample data to the non-use data buffer unit 405N in a case in which it is determined that they are not used. In a case of indicating an optional subsampling unit among the subsampling units 406_1 to 406_3, or in a case of collectively calling the subsampling units 406_1 to 406_3, the subsampling units 406_1 to 406_3 are simply referred to as a “subsampling unit 406”.

The subsampling rate designated in advance may be a fixed specific ratio (for example, 50%), or may be dynamically changed every time the subsampling operation is performed after learning of each decision tree.

As illustrated in FIG. 50 , the subsampling unit 406 includes a random number generation unit 411, a subsampling rate holding unit 412, a comparator 413, and a writing determining unit 414. The random number generation unit 411 is, for example, a module for generating a random number constituted of a Linear Feedback Shift Register (LFSR) and the like. The subsampling rate holding unit 412 is a module holding the subsampling rate designated in advance. The comparator 413 is a module that compares a random number generated by the random number generation unit 411 with the subsampling rate held by the subsampling rate holding unit 412, and determines whether to use the sample data output from the learning units 100_1 to 100_3 for learning of the next decision tree. That is, the sample data to be used for learning of the next decision tree is randomly selected from among pieces of the sample data output from the learning units 100_1 to 100_3 by the comparator 413. For example, the comparator 413 outputs information indicating whether to use the data for learning of the next decision tree to the writing determining unit 414 as a usage flag. An operation of outputting the usage flag performed by the random number generation unit 411 and the comparator 413 may be synchronized with a timing of inputting the data (the sample data and the state information).

The writing determining unit 414 is a module that outputs the sample data and the state information output from the learning units 100_1 to 100_3 (output from the FIFO units 403_1 to 403_3) to the use data buffer unit 405U or the non-use data buffer unit 405N in accordance with the usage flag output from the comparator 413. For example, the writing determining unit 414 outputs the input sample data and state information to the use data buffer unit 405U in a case in which the usage flag indicates that the data is used for learning of the next decision tree, and outputs the input sample data and state information to the non-use data buffer unit 405N in a case in which the usage flag indicates that the data is not used for learning of the next decision tree.

In a case of performing the operation of deriving the branch condition for the decision tree (learning operation for the decision tree), the writing determining unit 414 may input the sample data and information about the branching direction at the node as the learning target output from the FIFO units 403_1 to 403_3, and output the sample data to the use data buffer unit 405U functioning as the left buffer unit 404L or the non-use data buffer unit 405N functioning as the right buffer unit 404R as described later in accordance with the information about the branching direction.

Whether each piece of the sample data is used for learning of the next decision tree may be randomly selected corresponding to a predetermined subsampling rate, so that the subsampling unit 406 does not necessarily correspond to each learning unit 100 on a one-to-one basis.

The use data buffer unit 405U is a module that buffers the sample data and the state information output from the subsampling units 406_1 to 406_3 in order on a time-series basis to be used for learning of the next decision tree after learning of one decision tree. The use data buffer unit 405U includes an address counter and a data number counter (not illustrated).

Each of the address counter and the data number counter increments count (+1) every time the sample data and the state information to be used for learning of the next decision tree are input to the use data buffer unit 405U. When the data number counter indicates that the state information and the sample data having predetermined data volume is buffered, the use data buffer unit 405U writes the state information and the sample data having the data volume into one of the bank a and the bank b for storing the sample data to be used for learning of the next decision tree (hereinafter, referred to as “use bank” in some cases) for each predetermined block in ascending order of the address utilizing the address indicated by the address counter. After writing all pieces of the buffered sample data and state information into the use bank, the use data buffer unit 405U resets the data number counter.

In a case of performing the operation of deriving the branch condition for the decision tree (learning operation for the decision tree), the use data buffer unit 405U operates equivalently to the left buffer unit 404L in the fifth embodiment described above.

The non-use data buffer unit 405N is a module that buffers the sample data and the state information output from the subsampling units 406_1 to 406_3 in order on a time-series basis not to be used for learning of the next decision tree after learning of one decision tree. The non-use data buffer unit 405N includes an address counter and a data number counter (not illustrated).

The address counter and the data number counter increment count (+1) every time the state information and the sample data to be used for learning of the next decision tree are input to the non-use data buffer unit 405N. When the data number counter indicates that the sample data having predetermined data volume is buffered, the non-use data buffer unit 405N writes the sample data having the data volume into one of the bank a and the bank b for storing the sample data not to be used for learning of the next decision tree (hereinafter, referred to as “non-use bank” in some cases) for each predetermined block in descending order of the address utilizing the address indicated by the address counter. After writing all pieces of the buffered sample data and state information into the non-use bank, the non-use data buffer unit 405N resets the data number counter.

In a case of performing the operation of deriving the branch condition for the decision tree (learning operation for the decision tree), the non-use data buffer unit 405N operates equivalently to the right buffer unit 404R in the fifth embodiment described above.

The predetermined data volume as a basis of the timing at which the use data buffer unit 405U and the non-use data buffer unit 405N write the data into the bank a or the bank b of the data memory 30D is the same as the description about the left buffer unit 404L and the right buffer unit 404R in the fifth embodiment described above.

At the time of update processing for the gradient information performed by the learning unit 100 (classification module 50), the learning unit 100 (classification module 50) is required to write the sample data and the state information the gradient information of which is updated into the data memory 30D while reading out the sample data and the state information from the data memory 30D. In this case, by dividing the operation of reading-out and writing to be used for one data memory 30D on a time-series basis, a reading/writing operation for the data memory 30D can be implemented. At this point, it takes a long time to switch between a reading-out mode and a writing mode for the data memory 30D in some cases, but this overhead can be reduced by switching the mode for each block, or switching the mode in a longer unit by increasing the capacity of the FIFO units 402_1 to 402_3, the FIFO units 403_1 to 403_3, the use data buffer unit 405U, and the non-use data buffer unit 405N. Specifically, the reading-out mode and the writing mode may be switched for each data amount with which efficiency of transferring the data to the data memory 30D is maximized. The embodiment is not limited to switching between the reading-out mode and the writing mode for each data amount with which the transfer efficiency is maximized, and switching may be performed for each data amount with which the transfer efficiency is equal to or larger than a predetermined value.

The present embodiment describes the configuration of implementing the subsampling operation in decision tree learning by the gradient boosting decision tree (GBDT), but the configurations illustrated in FIG. 49 to FIG. 51 can be applied not only to the subsampling operation in the GBDT but also to the subsampling operation in general gradient boosting. In this case, gradient boosting is a method of repeatedly learning an optional machine learning model and updating the gradient information of each piece of the sample data. Examples of a model other than the decision tree in gradient boosting include a model using a method of least squares, linear regression, a support vector machine (SVM), and the like.

As described above, in the learning and discrimination device if according to the present embodiment, the sample data is held by the external memory (for example, the DRAM) instead of the SRAM inside the processing chip, the sample data to be used for learning of the next decision tree is buffered in the use data buffer unit 405U, and the sample data not to be used is buffered in the non-use data buffer unit 405N in the subsampling operation. In a case in which the sample data is buffered up to the volume determined in advance in each buffer unit, the sample data is written into the data memory 30 (bank a, bank b) for each predetermined block. Due to this, the sample data is accumulated up to certain data volume to be read and written in units of a certain size (block), so that finely divided random access like the SRAM is not made, and it is possible to achieve sufficient speed of the data memory 30D as an external memory (for example, the DRAM) for which random access cannot be made. Thus, data subsampling can be performed on a large amount of sample data in gradient boosting.

In a case in which the data memory is the SRAM inside the processing chip (FPGA), all pieces of the sample data stored in the SRAM are read out to update the gradient information after learning of the decision tree, and all pieces of the sample data are further read out thereafter to perform subsampling. In a case of performing this operation using the DRAM as an external memory, the processing is delayed. However, the learning and discrimination device if according to the present embodiment successively reads out the sample data stored in the data memory 30D to update the gradient information, and directly distributes the updated gradient information and the sample data to the data memory 30D to be stored therein depending on whether the gradient information and the sample data is used for learning of the next decision tree, so that the processing speed can be improved.

The configuration of the learning and discrimination device if according to the present embodiment is different from the learning and discrimination device 1 e according to the fifth embodiment described above in that the subsampling unit 406 is included therein, and the other configurations are the same. That is, the learning and discrimination device if according to the present embodiment has the configuration similar to that of the learning and discrimination device 1 e according to the fifth embodiment described above, and can implement the subsampling operation and the update processing for the gradient information that are required after learning of one decision tree with the configuration. Thus, the learning and discrimination device if according to the present embodiment has the same effect as the effect of the learning and discrimination device 1 e according to the fifth embodiment described above in the learning processing.

In the above description, the learning and discrimination device if according to the present embodiment stores both of the sample data and the state information including the gradient information in the external memory (for example, the DRAM), but the embodiment is not limited thereto. For example, the state information may be stored in the SRAM (an example of a first memory) inside the processing chip because the data amount thereof is smaller than that of the sample data, and the sample data may be stored in the external memory (second memory). In this case, the state information stored in the SRAM may be associated with the sample data stored in the external memory.

According to an embodiment, data subsampling can be performed on a large amount of sample data in gradient boosting.

The above-described embodiments are illustrative and do not limit the present invention. Thus, numerous additional modifications and variations are possible in light of the above teachings. For example, at least one element of different illustrative and exemplary embodiments herein may be combined with each other or substituted for each other within the scope of this disclosure and appended claims. Further, features of components of the embodiments, such as the number, the position, and the shape are not limited the embodiments and thus may be preferably set. It is therefore to be understood that within the scope of the appended claims, the disclosure of the present invention may be practiced otherwise than as specifically described herein.

The method steps, processes, or operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance or clearly identified through the context. It is also to be understood that additional or alternative steps may be employed.

Further, any of the above-described apparatus, devices or units can be implemented as a hardware apparatus, such as a special-purpose circuit or device, or as a hardware/software combination, such as a processor executing a software program.

Further, as described above, any one of the above-described and other methods of the present invention may be embodied in the form of a computer program stored in any kind of storage medium. Examples of storage mediums include, but are not limited to, flexible disk, hard disk, optical discs, magneto-optical discs, magnetic tapes, nonvolatile memory, semiconductor memory, read-only-memory (ROM), etc.

Alternatively, any one of the above-described and other methods of the present invention may be implemented by an application specific integrated circuit (ASIC), a digital signal processor (DSP) or a field programmable gate array (FPGA), prepared by interconnecting an appropriate network of conventional component circuits or by a combination thereof with one or more conventional general purpose microprocessors or signal processors programmed accordingly.

Each of the functions of the described embodiments may be implemented by one or more processing circuits or circuitry. Processing circuitry includes a programmed processor, as a processor includes circuitry. A processing circuit also includes devices such as an application specific integrated circuit (ASIC), digital signal processor (DSP), field programmable gate array (FPGA) and conventional circuit components arranged to perform the recited functions. 

What is claimed is:
 1. A learning device configured to perform learning by gradient boosting, the learning device comprising: a data memory configured to store learning data for learning a model by the gradient boosting and gradient information corresponding to the learning data; circuitry configured to perform a process of learning the model by gradient boosting, the process comprising, for each of a plurality of iterations: learn a first model using the learning data stored in the data memory; and perform each of the plurality of iterations, wherein a first iteration uses the first model as the current model and each subsequent iteration uses a previous next model as the current model, each iteration comprising: updating gradient information of each learning data based on a learned current model; determining, for each learning data, whether to use the learning data corresponding to the updated gradient information for learning of a next model after learning of the first model based on a subsampling rate, wherein the subsampling rate is a ratio of learning data used for the learning of the first model; dividing, based on the determining, the learning data into first learning data determined to be used for learning of the next model and second learning data determined not to be used for learning of the next model; outputting data into one of a first buffer and a second buffer based on the dividing; using data of the first buffer for learning the next model; and outputting data of the first buffer and the second buffer into the data memory; the first buffer, which is configured to buffer the first learning data and first gradient information, of the gradient information, corresponding to the first learning data up to a volume determined in advance of performing the process of learning the model; and the second buffer, which is configured to buffer the second learning data and second gradient information, of the gradient information, corresponding to the second learning data up to the volume determined in advance of performing the process of learning the model, wherein the circuitry is further configured to output the first learning data to the first buffer and, in parallel, to output the second learning data to the second buffer, the first buffer is configured to write the first learning data and the first gradient information into the data memory for each predetermined block when buffering the first learning data and the first gradient information up to the volume determined in advance of performing the process of learning the model, and the second buffer is configured to write the second learning data and the second gradient information into the data memory for each predetermined block when buffering the second learning data and the second gradient information up to the volume determined in advance of performing the process of learning the model.
 2. The learning device according to claim 1, wherein the circuitry is configured to read out the learning data for each predetermined block, when reading out the learning data from the data memory to update the gradient information.
 3. The learning device according to claim 1, wherein the data memory comprises: a first bank region for storing the first learning data and the first gradient information; and a second bank region for storing the second learning data and the second gradient information.
 4. The learning device according to claim 3, wherein the data memory includes two data memories, and one of the two data memories includes the first bank region, and the other one of the two data memories includes the second bank region.
 5. The learning device according to claim 1, wherein the data memory comprises a dynamic random access memory (DRAM).
 6. The learning device according to claim 1, wherein the data memory comprises: a first memory configured to store the gradient information, the first memory comprising a memory inside a processing chip; and a second memory configured to store the learning data, the second memory comprising a memory outside the processing chip.
 7. The learning device according to claim 6, wherein the first memory comprises a static random access memory (SRAM), and the second memory comprises a DRAM.
 8. The learning device according to claim 1, wherein the volume determined in advance is determined based on a burst length of the data memory.
 9. The learning device according to claim 1, wherein an operation of reading-out and writing is divided to be performed on a time-series basis in the data memory.
 10. The learning device according to claim 9, wherein the operation of reading-out and writing is divided to be performed on the time-series basis such that transfer efficiency of the operation of reading-out and writing is equal to or larger than a predetermined value in the data memory.
 11. The learning device according to claim 1, wherein the circuitry includes a learning circuit configured to learn the model, an update circuit configured to update the gradient information, and a subsampling circuit configured to determine whether to use the learning data, and an operating frequency of processing performed by the learning circuit and the update circuit is different from an operating frequency of processing performed by the subsampling circuit, the first buffer, and the second buffer.
 12. The learning device according to claim 1, wherein the circuitry includes a learning circuit configured to learn the model, and an update circuit configured to update the gradient information, and the learning circuit include a plurality of learning circuits and the update circuit includes a plurality of update circuits.
 13. The learning device according to claim 12, wherein the circuitry is further configured to read out the learning data from the data memory for each predetermined block, and distribute learning data included in each block to the learning circuits in order.
 14. The learning device according to claim 1, wherein the circuitry is configured to learn a decision tree as the model by a gradient boosting decision tree as the gradient boosting.
 15. The learning device according to claim 14, wherein the circuitry is configured to determine whether to cause the learning data stored in the data memory to branch to one node or to another node of lower nodes of a node of the decision tree based on a branch condition for the node, the first buffer is configured to buffer first learning data determined to branch to the one node by the circuitry up to the volume determined in advance, the second buffer is configured to buffer second learning data determined to branch to the other node by the learning up to the volume determined in advance, and the first buffer and the second buffer are configured to write the corresponding first and second learning data into continuous addresses of the data memory for each predetermined block when buffering up to the volume determined in advance.
 16. A learning method of performing learning by gradient boosting, the learning method comprising: performing a process of learning a model, which is stored in a data memory configured to store learning data and gradient information corresponding to the learning data, by the gradient boosting, the process comprising, for each of a plurality of iterations: learning a first model using the learning data stored in the data memory; and performing each of the plurality of iterations, wherein a first iteration uses the first model as the current model and each subsequent iteration uses a previous next model as the current model, each iteration comprising: updating gradient information of each learning data based on a learned current model; determining, for each learning data, whether to use the learning data corresponding to the updated gradient information for learning of a next model after learning of the first model based on a subsampling rate, wherein the subsampling rate is a ratio of learning data used for the learning of the first model; dividing, based on the determining, the learning data into first learning data determined to be used for learning of the next model and second learning data determined not to be used for learning of the next model; outputting data into one of a first buffer and a second buffer based on the dividing; using data of the first buffer for learning the next model; and outputting data of the first buffer and the second buffer into the data memory; buffering the first learning data and first gradient information, of the gradient information, corresponding to the first learning data in the first buffer up to a volume determined in advance of performing the process of learning the model; buffering the second learning data and second gradient information, of the gradient information, corresponding to the second learning data in the second buffer up to the volume determined in advance of performing the process of learning the model; writing the first learning data and the first gradient information into the data memory for each predetermined block when buffering the first learning data and the first gradient information up to the volume determined in advance of performing the process of learning the model; and writing the second learning data and the second gradient information into the data memory for each predetermined block when buffering the second learning data and the second gradient information in the second buffer up to the volume determined in advance of performing the process of learning the model, wherein the first learning data is output to the first buffer while, in parallel, the second learning data is output to the second buffer. 